Planar capacitor memory cell and its applications

• US 7,209,384 B1
• Filed: 12/08/2005
• Issued: 04/24/2007
• Est. Priority Date: 12/08/2005
• Status: Expired due to Fees

• Current Assignee: Juhan Kim
• Original Assignee: Juhan Kim
• Inventors: Kim, Juhan
• Primary Examiner(s): PHUNG, ANH K
• Application Number:
  US11/164,872
• Time in Patent Office: 502 Days
• Field of Search: 365/175, 365/105, 365/187, 365/149
• US Class Current: 365/175
• CPC Class Codes: G11C 11/22 using ferroelectric elements
• CPC Class Codes: G11C 11/24 using capacitors G11C11/22 takes precedence; using a combination of semiconductor devices and capacitors G11C11/34, e.g. G11C11/40
• CPC Class Codes: G11C 11/404 with one charge-transfer gate, e.g. MOS transistor, per cell
• CPC Class Codes: G11C 11/405 with three charge-transfer gates, e.g. MOS transistors, per cell
• CPC Class Codes: G11C 11/4067 for memory cells of the bipolar type
• CPC Class Codes: G11C 11/4085 Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 11/4094 Bit-line management or control circuits
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 15/043 using capacitive charge storage elements
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2211/4016 Memory devices with silicon-on-insulator cells
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/106 Data output latches
• CPC Class Codes: G11C 7/12 Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 21/84 the substrate being other than a semiconductor body, e.g. being an insulating body
• CPC Class Codes: H01L 27/0688 : Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/101 : including resistors or capacitors only
• CPC Class Codes: H01L 27/105 : including field-effect components
• CPC Class Codes: H01L 27/1203 : the substrate comprising an insulating body on a semiconductor body, e.g. SOI three-dimensional layout H01L27/0688
• CPC Class Codes: H01L 27/1214 : comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H10B 12/00 : Dynamic random access memory [DRAM] devices
• CPC Class Codes: H10B 12/10 : DRAM devices comprising bipolar components
• CPC Class Codes: H10B 99/00 : Subject matter not provided for in other groups of this subclass

Abstract

A capacitor memory is realized, wherein a capacitor stores data and a diode controls to store data “1” or “0”. Diode has four terminals wherein first terminal serves as word line, second terminal serves as storage node, third terminal is floating, and fourth terminal serves as bit line, wherein back channel effect is suppressed adding additional ions in the bottom side of third terminal or applying negative voltage in the well or substrate. A capacitor plate couples to second terminal, which plate has no coupling region to first, third and fourth terminal. With no coupling, the inversion layer of plate in the storage node is isolated from the adjacent nodes. In doing so, the plate can swing ground level to positive supply level to write. As a result, no negative generator is required for controlling plate. Word line and bit line keep ground level during standby, and rise to supply level for read or write operation. In this manner, no holding current is required during standby, and operating current is dramatically reduced with no negative generator. Write has a sequence to clear the state of cell before writing to store data regardless of previous state. Refresh cycle is periodically asserted to sustain data. The present invention can be applied for destructive read, or for nondestructive read adding pull-down device to bit line. The height of cell is almost same as control circuit on the bulk or SOI wafer.

Claims

1. A random access memory, comprising:

memory cell, wherein a capacitor stores data and a diode controls to store data “

1”

(on) or “

0”

(off); and

the diode, wherein includes four terminals, the first terminal is p-type and serves as a word line, the second terminal is n-type and serves as a storage node, the third terminal is p-type and floating, and the fourth terminal is n-type and serves as a bit line; and

plate of capacitor couples to the second terminal, which plate has no coupling region to first, third and fourth terminal; and

the diode is planar type which is horizontally formed on the surface of the wafer;

capacitor is formed on the second terminal of the diode by adding insulator between the second terminal and the plate, thus the height of the memory cell is almost same as that of MOS transistor in the chip; and

pull-down transistor, wherein is connected to the fourth terminal of the diode through the bit line, and the pull-down transistor sustains the current path from the word line through the diode when the storage node voltage is lower than the word line voltage minus built-in voltage of the diode, which establishes the forward bias from the word line (first terminal) to the storage node (second terminal) by asserting the word line, thus the forward bias turns on the diode and sets up the current path from the word line to the pull-down transistor, as a result the diode generates a current flow, which is data “

1”

as a current output, and when the storage node voltage is higher than the word line voltage, the forward bias is not established from the word line to the storage node, as a result the diode does not generate a current flow through the pull-down transistor, which is data “

0”

with no current output.

2. The random access memory of claim 1, wherein the insulator of the capacitor includes higher dielectric constant than that of control circuit in the chip.

3. The random access memory of claim 1, wherein the diode is formed from silicon diode.

4. The random access memory of claim 1, wherein is the diode formed from compound semiconductor.

5. The random access memory of claim 1, wherein is the diode formed from germanium.

6. The random access memory of claim 1, wherein can be implemented an alternative embodiment with reverse configuration;

and the diode, wherein includes four terminals, the first terminal is n-type and serves as a word line, the second terminal is p-type and serves as a storage node, the third terminal is n-type and floating, and the fourth terminal is p-type and serves as a bit line;

plate of capacitor couples the second terminal, which plate has no coupling region to first, third and fourth terminal; and

pull-up transistor is connected to the fourth terminal of the diode through the bit line.