Memory device with clock multiplier circuit

• US 7,209,397 B2
• Filed: 03/31/2005
• Issued: 04/24/2007
• Est. Priority Date: 04/24/2001
• Status: Expired due to Term

• Current Assignee: Rampart Asset Management LLC
• Original Assignee: Rambus Inc.
• Inventors: Perego, Richard E., Tsern, Ely K., Hampel, Craig E., Ware, Frederick A.
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): Luu; Pho M.
• Application Number:
  US11/094,137
• Publication Number:
  US 20050169097A1
• Time in Patent Office: 754 Days
• Field of Search: 365/194, 365/233, 365/191, 365/221, 327/156
• US Class Current: 365/194
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/105 in which the distribution is at least partially optical
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 13/1684 using multiple buses
• CPC Class Codes: G06F 13/1689 Synchronisation and timing concerns synchronisation on a memory bus G06F13/4234
• CPC Class Codes: G06F 13/1694 Configuration of memory controller to different memory types
• CPC Class Codes: G06F 13/4086 Bus impedance matching, e.g. termination
• CPC Class Codes: G06F 13/4243 with synchronous protocol
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0658 Controller construction arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/409 Read-write [R-W] circuits
• CPC Class Codes: G11C 11/4096 Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches
• CPC Class Codes: G11C 29/02 Detection or location of defective auxiliary circuits, e.g. defective refresh counters
• CPC Class Codes: G11C 29/022 in I/O circuitry
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50008 of impedance
• CPC Class Codes: G11C 29/50012 of timing
• CPC Class Codes: G11C 5/063 : Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/04 : with means for avoiding disturbances due to temperature effects
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 : Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/22 : Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/222 : Clock generating, synchronizing or distributing circuits within memory device
• CPC Class Codes: G11C 8/18 : Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals

Abstract

A memory device having a clock multiplier circuit. The memory device includes a clock generating circuit to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of the first frequency. The memory device includes a data receive circuit to receive data at the frequency of the second clock signal and may also include a data transmit circuit to transmit data at the frequency of the second clock signal. Further, the clock generating circuit may additionally generate a third clock signal having a third frequency that is also a multiple of the first frequency, the third clock signal being supplied to a control circuit of the memory device to time the reception of control and/or address signals therein. In a particular embodiment the second frequency is a four-times or eight-times multiple of the first frequency, and the third frequency is a two-times multiple of the first frequency.

Claims

1. A memory device comprising:

clock generation circuitry to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of, and higher than, the first frequency; and

a data receive circuit to receive data from an external signal path at the second frequency of the second clock signal.

2. The memory device of claim 1 wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the second clock signal, and wherein the second frequency is an eight-times multiple of the first frequency.

3. The memory device of claim 2 wherein the data receive circuit comprises a serial-input register that is loaded with data at the second frequency and a parallel-input register coupled to receive data from the serial-input register, and wherein the clock generation circuitry further comprises a second phase locked loop circuit to generate a third clock signal having the first frequency, the third clock signal being provided to the parallel-input register to transfer data from the serial-input register to the parallel-input register at the first frequency.

4. The memory device of claim 1 wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the second clock signal, and wherein the second frequency is a four-times multiple of the first frequency.

5. The memory device of claim 1 further comprising a data transmit circuit to transmit data at the second frequency of the second clock signal.

6. The memory device of claim 5 wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the second clock signal, and wherein the second frequency is a eight-times multiple of the first frequency.

7. The memory device of claim 6 wherein the data transmit circuit comprises a serial-output register to output data at the second frequency, and a parallel-output register to provide data to the serial-output register, and wherein the clock generation circuitry further comprises a second phase locked loop circuit to generate a third clock signal having the first frequency, the third clock signal being provided to the parallel-output register to load data into the parallel-output register at the first frequency.

8. The memory device of claim 1 further comprising a circuit to receive control information at the frequency of a third clock signal, and wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the third clock signal at a third frequency that is a two-times multiple of the first frequency.

9. The memory device of claim 8 wherein the control information includes address information.

10. The memory device of claim 8 wherein the circuit to receive control information comprises a serial-input register that is loaded with data at the third frequency and a parallel-input register coupled to receive data from the serial-input register, and wherein the clock generation circuitry further comprises a second phase locked loop circuit to generate a fourth clock signal having the first frequency, the fourth clock signal being provided to parallel-input register to transfer data from the serial-input register to the parallel-input register at the first frequency.

11. The memory device of claim 1, further comprising a memory core circuit to receive/transmit memory signals at the first frequency.

12. The memory device of claim 11, wherein the clock generation circuitry comprises a phase locked loop circuit to generate a third clock signal having the first frequency and wherein the memory core circuit is to receive/transmit memory signals in response to the third clock signal.

13. A memory device comprising:

clock generation circuitry to receive a first clock signal having a first frequency and to generate a second clock signal having a second frequency that is a multiple of, and higher than, the first frequency; and

a data transmit circuit to transmit data on an external signal path at the second frequency of the second clock signal.

14. The memory device of claim 13, wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the second clock signal, and wherein the second frequency is an eight-times multiple of the first frequency.

15. The memory device of claim 14, wherein the wherein the data transmit circuit comprises a serial-output register to output data at the second frequency, and a parallel-output register to provide data to the serial-output register, and wherein the clock generation circuitry further comprises a second phase locked loop circuit to generate a third clock signal having the first frequency, the third clock signal being provided to the parallel-output register to load data into the parallel-output register at the first frequency.

16. The memory device of claim 13, wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the second clock signal, and wherein the second frequency is a four-times multiple of the first frequency.

17. The memory device of claim 13 further comprising an control circuit to receive control information at the frequency of a third clock signal, wherein the clock generation circuitry comprises a first phase locked loop circuit to generate the third clock signal at a third frequency that is a two-times multiple of the first frequency.

18. The memory device of claim 17 wherein the control information includes address information.

19. The memory device of claim 17 wherein the circuit to receive control information comprises a serial-input register that is loaded with data at the third frequency and a parallel-input register coupled to receive data from the serial-input register, and wherein the clock generation circuitry further comprises a second phase locked loop circuit to generate a fourth clock signal having the first frequency, the fourth clock signal being provided to the parallel-input register to transfer data from the serial-input register to the parallel-input register at the first frequency.

20. The memory device of claim 13 further comprising a memory core circuit to receive/transmit memory signals at the first frequency.

21. The memory device of claim 20 wherein the clock generation circuitry comprises a phase locked loop circuit to generate a third clock signal having the first frequency and wherein the memory core circuit is to receive/transmit memory signals in response to the third clock signal.

22. A memory device comprising:

clock generation circuitry to receive a first clock signal having a first frequency and to generate a second clock signal having a frequency that is an eight-times multiple of the first frequency and a third clock signal having a frequency that is a two-times multiple of the first frequency;

a data receive circuit to receive data at the frequency of the second clock signal;

a data transmit circuit to transmit data at the frequency of the second clock signal; and

a circuit to receive control information at the frequency of the third clock signal.