DSO timing source transient compensation
First Claim
1. A method of compensating for timing source transients caused by misalignment of first and second clock signals, the method comprising the steps of:
- monitoring a control signal transmitted using the second clock signal for frame position information for the first clock signal;
responsive to detection of frame position information, determining whether the first and second clock signals are misaligned; and
responsive to a determination that the first and second signals are misaligned, periodically temporarily altering one clock period of the first clock signal until the first and second signals are realigned.
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Accused Products
Abstract
System and method for compensating for DS0 timing source transients, such as may occur during a switchover to a new external reference, is described. In one embodiment, an SFI control signal is monitored for embedded frame position information. When the frame position information is initially detected, a 10-bit frame clock counter is reset to zero. The counter is then incremented using an 8.192 MHz clock. From that point on, each time the SFI frame position information is detected, the value of the frame clock counter is checked. If the counter value is zero, the counter continues to run freely. If the counter value is non-zero and the most significant bit (“MSB”) thereof is zero, the count of the frame clock counter is held for one clock period. If the counter value is non-zero and the MSB thereof is one, the count of the frame clock counter is advanced by a value of two, rather than one, for one clock period.
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Citations
23 Claims
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1. A method of compensating for timing source transients caused by misalignment of first and second clock signals, the method comprising the steps of:
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monitoring a control signal transmitted using the second clock signal for frame position information for the first clock signal; responsive to detection of frame position information, determining whether the first and second clock signals are misaligned; and responsive to a determination that the first and second signals are misaligned, periodically temporarily altering one clock period of the first clock signal until the first and second signals are realigned. - View Dependent Claims (2, 3)
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4. A method of compensating for timing source transients caused by misalignment of first and second clock signals, the method comprising the steps of:
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monitoring a control signal transmitted using the second clock signal for frame position information for the first clock signal; responsive to detection of frame position information, resetting a counter to zero; causing the counter to increment using the first clock signal; continuing to monitor the control signal for frame position information; responsive to each subsequent detection of frame position information; determining a value of the counter; if the value of the counter is non-zero and the most significant bit (“
MSB”
) of the counter is zero, advancing the value of the counter by more than one count for one clock cycle; andif the value of the counter is non-zero and the MSB of the counter is non-zero, holding the value of the counter for at least one clock cycle. - View Dependent Claims (5, 6, 7, 8, 9, 10)
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11. A system for compensating for timing source transients caused by misalignment of first and second clock signals, the system comprising:
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means for monitoring a control signal transmitted using the second clock signal for frame position information for the first clock signal; means responsive to detection of frame position information for resetting a counter to zero; means for causing the counter to increment using the first clock signal; means for continuing to monitor the control signal for frame position information; means responsive to each subsequent detection of frame position information for determining a value of the counter; means responsive to a determination that the value of the counter is non-zero and the most significant bit (“
MSB”
) of the counter is zero for advancing the value of the counter by more than one count for one clock cycle; andmeans responsive to a determination that the value of the counter is non-zero and the MSB of the counter is non-zero for holding the value of the counter for at least one clock cycle. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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18. Apparatus for compensating for timing source transients caused by misalignment of first and second clock signals in a telecommunications signaling server, the apparatus comprising:
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logic for monitoring a control signal transmitted using the second clock signal for frame position information for the first clock signal; a counter connected to the monitoring logic; logic responsive to detection of frame position information for resetting the counter to zero; wherein, subsequent to the resetting, the counter increments using the first clock signal; wherein the monitoring logic continues to monitor the control signal for frame position information; and wherein responsive to each subsequent detection of frame position information by the monitoring logic, the monitoring logic determines a value of the counter and, if the value of the counter is non-zero and the most significant bit (“
MSB”
) of the counter is zero, the value of the counter is advanced by more than one count for one clock cycle, and, if the value of the counter is non-zero and the MSB of the counter is non-zero, the value of the counter is held for at least one clock cycle. - View Dependent Claims (19, 20, 21, 22, 23)
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Specification