Apparatus and method for data deskew

• US 7,209,531 B1
• Filed: 03/26/2003
• Issued: 04/24/2007
• Est. Priority Date: 03/26/2003
• Status: Active Grant

• Current Assignee: Marvell Asia Pte Limited (Marvell Technology Group Limited)
• Original Assignee: Cavium, LLC (Marvell Technology Group Limited)
• Inventors: Kessler, Richard E., Katz, Daniel A., Xanthopoulos, Thucydides
• Primary Examiner(s): TRAN, KHANH C
• Application Number:
  US10/397,083
• Time in Patent Office: 1,490 Days
• Field of Search: 375/371, 375/373, 375/355, 370/503, 370/516, 370/517, 370/519, 327/141, 327/161
• US Class Current: 375/371
• CPC Class Codes: H03K 5/133 using a chain of active delay devices
• CPC Class Codes: H04L 7/005 Correction by an elastic buffer
• CPC Class Codes: H04L 7/0338 the correction of the phase error being performed by a feed forward loop
• CPC Class Codes: H04L 7/10 Arrangements for initial synchronisation

Abstract

A deskew circuit utilizing a coarse delay adjustment and fine delay adjustment centers the received data in a proper data window and aligns the data for proper sampling. In one scheme, bit state transitions of a training sequence for SPI-4 protocol is used to adjust delays to align the transition points.

Claims

1. An apparatus comprising:

a coarse delay unit to receive a bit pattern, which may be skewed in timing with a corresponding reference clocking signal, and to align sampling of bits of the bit pattern to within a same selected bit-time frame; and

a fine delay unit to receive the bit pattern and to align sampling of bits of the bit pattern away from an edge of the selected bit-time frame, the coarse and fine delay units to perform a deskew operation by aligning bits of a bit pattern to within the same selected bit-time frame and positioned toward a center of the selected bit-time frame.

2. The apparatus of claim 1, wherein said coarse delay unit to select a bit-time frame of a latest occurring bit of the bit pattern as the selected bit-time frame and to delay sampling of bits of the bit pattern aligned to an earlier bit-time frame.

3. The apparatus of claim 1, wherein said fine delay unit to align a particular bit within the selected bit-time frame by incrementing or decrementing delay to reposition the particular bit toward the center of the selected bit-time frame.

4. The apparatus of claim 1, wherein said fine delay unit to align a particular bit within the selected bit-time frame by following a sequence of incrementing and decrementing incremental delay offsets to reposition the particular bit toward the center of the selected bit-time frame.

5. The apparatus of claim 4, wherein the sequence of delay offsets are to be increased in offset value to determine the position of the particular bit in relation to an edge of the bit-time frame and to reposition the particular bit away from the edge.

6. The apparatus of claim 4, wherein the sequence of delay offsets are to be increased in offset value to determine the position of the particular bit in relation to leading and trailing edges of the bit-time frame and to reposition the particular bit approximately near a center position of the bit-time frame.

7. The apparatus of claim 4, further including a macro sequencer to control the delay offset to be applied to reposition the particular bit.

8. The apparatus of claim 1, wherein the deskew operation is to be performed on a bit pattern specified by a System Packet Interface protocol.

9. The apparatus of claim 1, wherein a state transition change of a training sequence signal is to be used as the bit pattern to align the sampling of the bits for the deskew operation.

10. An apparatus comprising:

a coarse delay unit to receive a bit pattern, which may be skewed in timing with a corresponding reference clocking signal, and to align sampling of bits of the bit pattern to within a same selected bit-time frame by selecting a bit-time frame of a latest occurring bit of the bit pattern as the selected bit-time frame and said coarse delay unit to delay sampling of bits of the bit pattern aligned to any earlier bit-time frame until occurrence of the selected bit-time frame; and

a fine delay unit to receive the bit pattern and to align sampling of bits of the bit pattern away from an edge of the selected bit-time frame by introducing more or less delay offset to each individual bit to individually reposition each bit away from an edge and toward a center of the bit-time frame, the coarse and fine delay units to perform a deskew operation by aligning bits of a bit pattern to within the same selected bit-time frame and each bit sampling time moved toward a center of the selected bit-time frame.

11. The apparatus of claim 10, wherein the deskew operation to use a bit state transition of a reference bit pattern to identify bit skew and the bit state transitions are then used to align the bits to a deskewed sampling point.

12. The apparatus of claim 11, wherein the reference bit pattern is a training sequence signal of a data packet transfer protocol.

13. The apparatus of claim 11, wherein the reference bit pattern is a training sequence signal of a System Packet Interface protocol.

14. The apparatus of claim 11, wherein said fine delay unit to align a particular bit within the selected bit-time frame by following a sequence of incrementing and decrementing delay offsets to reposition the particular bit toward the center of the selected bit-time frame.

15. The apparatus of claim 14, wherein the sequence of delay offsets are to be increased in offset value to determine the position of the particular bit in relation to an edge of the bit-time frame and to reposition the particular bit away from the edge and toward the center.

16. The apparatus of claim 14, wherein the sequence of delay offsets for the particular bit are to be obtained by using a serial delay line and selecting an appropriate delay tap.

17. The apparatus of claim 16, wherein the sequence of delay offsets are to be determined by stage delays of the serial delay line.

18. The apparatus of claim 17 wherein a single stage delay for the delay line is in the approximate range of 70–

120 picoseconds.

19. The apparatus of claim 14 further including a macro sequencer to control the value of the delay offset to be applied to reposition the particular bit.

20. A deskew method comprising:

receiving an input bit pattern which may be skewed in timing to a corresponding reference clocking signal;

applying a coarse delay adjustment to skewed bits of the pattern to place the bits of a pattern in a same selected bit-time frame to sample the bits of the pattern in the same selected bit-time frame; and

applying a fine delay adjustment individually to bits of the pattern to position the bits of the pattern toward a center position of the selected bit-time frame to align the bits to a sampling position away from an edge of the bit-time frame.

21. The deskew method of claim 20 further including detecting bit state transitions of a training sequence signal and using the bit state transitions to apply the coarse and fine delay adjustments to align the bits into a proper bit-time frame and away from edges of the bit-time frame.

22. The deskew method of claim 21, wherein said applying the coarse delay adjustment places the bits into the bit-time frame of a latest transitioning bit of the bit pattern.

23. The deskew method of claim 22, wherein said applying the fine delay adjustment applies a sequence of incremental delay offsets to identify an edge of the bit-time frame.

24. The deskew method of claim 23, wherein said detecting and using bit state transitions of a training sequence detects and uses a System Packet Interface protocol training sequence signal.

25. A system comprising:

a link layer device to transmit data;

a deskew device to deskew data received from said link layer device, said deskew device including;

(a) a coarse delay unit to receive a bit pattern, which may be skewed in timing with a corresponding reference clocking signal, and to align sampling of bits of the bit pattern to within a same selected bit-time frame by selecting a bit-time frame of a latest occurring bit of the bit pattern as the selected bit-time frame and said coarse delay unit to delay sampling of bits of the bit pattern aligned to any earlier bit-time frame until occurrence of the selected bit-time frame;

(b) a fine delay unit to receive the bit pattern and to align sampling of bits of the bit pattern away from an edge of the selected bit-time frame by introducing more or less delay offset to each individual bit to individually reposition each bit away from an edge and toward a center of the bit-time frame, the coarse and fine delay units to perform a deskew operation by aligning bits of a bit pattern to within the same selected bit-time frame and each bit sampling time moved toward a center of the selected bit-time frame; and

a processor coupled to receive deskew data from said deskew device.

26. The system of claim 25, wherein the deskew operation includes using a bit state transition of a reference bit pattern to identify bit skew, the reference bit pattern is a training sequence signal of a data packet transfer protocol.

27. The system of claim 26, wherein the bit state transitions are used to align the bits to a deskewed sampling point.

28. The system of claim 25, wherein the deskew operation includes using a bit state transition of a reference bit pattern to identify bit skew, the reference bit pattern is a training sequence signal of a System Packet Interface protocol.

29. The system of claim 28 wherein the bit state transitions are used to align the bits to a deskewed sampling point.

30. The system of claim 25, wherein said fine delay unit to align a particular bit within the selected bit-time frame by following a sequence of incrementing and decrementing delay offsets to reposition the particular bit toward the center of the selected bit-time frame.

31. The system of claim 30 wherein the sequence of delay offsets are to be increased in offset value to determine the position of the particular bit in relation to an edge of the bit-time frame and to reposition the particular bit away from the edge and toward the center.

32. The system of claim 31 wherein said deskew device further including a macro sequencer to control the value of the delay offset to be applied to reposition the particular bit.