Continuous interleave burst access
First Claim
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1. A method, comprising:
- forming a synchronous memory device having addressable memory cells adapted to access a sequence of memory cells in response to an externally provided start address;
forming a microprocessor coupled to the synchronous memory device and adapted to initiate a first data read operation at a first memory cell address; and
forming a memory controller in the synchronous memory device adapted to produce a second start address in response to the externally provided start address and initiate a read operation in anticipation of a second data read operation at a new memory cell start address provided from the microprocessor, such that data stored at the second start address is output on an external data communication connection of the synchronous memory device following data output by the first data read operation to maintain an active data output stream between the first data read operation and a second data read operation requested by the microprocessor at the new memory cell start address for each first data read operation.
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Abstract
A system is described which uses a burst access memory and a memory controller to anticipate the memory address to be used in future data read operations as requested by a microprocessor. Either the memory controller or the memory device initiates a burst read operation starting at a memory address generated thereby. The microprocessor can, therefore, wait to initiate a data read without suffering a time delay.
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Citations
40 Claims
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1. A method, comprising:
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forming a synchronous memory device having addressable memory cells adapted to access a sequence of memory cells in response to an externally provided start address;
forming a microprocessor coupled to the synchronous memory device and adapted to initiate a first data read operation at a first memory cell address; andforming a memory controller in the synchronous memory device adapted to produce a second start address in response to the externally provided start address and initiate a read operation in anticipation of a second data read operation at a new memory cell start address provided from the microprocessor, such that data stored at the second start address is output on an external data communication connection of the synchronous memory device following data output by the first data read operation to maintain an active data output stream between the first data read operation and a second data read operation requested by the microprocessor at the new memory cell start address for each first data read operation. - View Dependent Claims (2, 3, 4, 5)
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6. A method, comprising:
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forming a microprocessor;
forming a burst access memory having addressable memory cells for providing data from a series of memory cells in response to a first read request from the microprocessor, the read request including a first start memory cell address; andforming address generation circuitry included in the burst access memory for generating a second start memory cell address in response to the first start memory cell address and initiating a burst read operation in anticipation of a second read request from the microprocessor, such that data stored at the second start address is output on an external data communication connection of the burst access memory following data output by the first read request to maintain an active data output stream between the first read request and a second read request by the microprocessor at a new memory cell start address for each first read request. - View Dependent Claims (7, 8, 9)
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10. A method, comprising:
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forming a burst access memory; forming a processor to request a first read operation followed by a second read operation, the processor to provide a first start address to the burst access memory for the first read operation and to provide a second start address to the burst access memory for the second read operation; forming an address generator to detect the first start address and provide an anticipated start address to the burst access memory in response to the first start address; wherein the burst access memory is adapted to output a first burst output in response to the first start address and to output an anticipated burst output in response to the anticipated start address; and wherein, when the anticipated start address corresponds to the second start address, the anticipated burst output follows the first burst output and maintains an active data output stream from the burst access memory from the first read operation to the second read operation. - View Dependent Claims (11, 12, 13)
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14. A method, comprising:
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forming addressable memory cells; forming a processor adapted to generate a first start address to read the memory cells; and forming a memory controller adapted to receive the first start address, to output a first data series from the addressable memory cells to the processor in response to receiving the first start address, to generate an anticipated start address in response to receiving the first start address, and to output an anticipated data series from the addressable memory cells such that the anticipated data series follows the first data series to maintain an active data output stream from the addressable memory cells to the processor. - View Dependent Claims (15, 16, 17, 18, 19)
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20. A method, comprising:
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forming a memory device, including addressable memory cells and control circuitry to provide burst outputs from the addressable memory cells in response to an address; forming a processor to request a first burst read operation from the addressable memory cells followed by a second burst read operation from the addressable memory cells, the processor to provide a first address to the control circuitry of the memory device for the first burst read operation and to provide a second address to the control circuitry of the memory device for the second burst read operation, the memory device to output a first burst output in response to the first address; and forming an address generator to provide an anticipated address to the memory device based on the first address such that the memory device outputs an anticipated burst output, wherein when the anticipated address corresponds to the second address, the memory device is adapted to maintain an active data stream for the first burst read operation and the second burst read operation. - View Dependent Claims (21, 22)
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23. A method, comprising:
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forming a microprocessor; and forming a synchronous memory device, including; forming a memory cell array; forming address circuitry coupled to the memory cell array; and forming control circuitry coupled to the address circuitry and to the memory cell array; wherein the microprocessor is adapted to provide a first start address to the synchronous memory device; wherein the control circuitry is adapted to provide a first burst output from the memory cell array to the microprocessor in response to the first start address; wherein the control circuitry is adapted to provide an anticipated start address in response to the first start address in anticipation of a second start address from the microprocessor; wherein, in response to the anticipated start address, the control circuitry is adapted to initiate an anticipated burst output from the memory cell array; and wherein the anticipated burst output follows the first burst output and maintains an active data output stream to the microprocessor for the first externally-provided start address and the second externally-provided start address. - View Dependent Claims (24, 25, 26, 27, 28, 29)
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30. A method, comprising:
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forming a microprocessor; and forming a synchronous memory device, including; forming addressable memory cells; and forming a memory controller coupled to the memory cells; wherein the microprocessor is adapted to provide read requests to the synchronous memory device; wherein the memory controller is adapted to output a data series from the addressable memory cells to the microprocessor in response to the read requests beginning with a start address contained within the read requests; wherein the memory controller is adapted to output a first data series to the microprocessor in response to a first external read request beginning with a first start address contained within the first external read request; wherein, in response to the first start address, the memory controller is adapted to initiate an output of an anticipated data series to the microprocessor beginning with an anticipated start address in anticipation of a second read request from the microprocessor; wherein, in response to the second read request from the microprocessor that begins with a second start address, the memory controller is adapted to compare the second start address to the anticipated start address and to continue to output the anticipated data series as a second data series when the second start address is the same as the anticipated start address; and wherein the second data series follows the first data series to maintain an active data output stream on the external output connection. - View Dependent Claims (31, 32, 33, 34, 35, 36)
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37. A method, comprising:
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forming a burst access memory, including; forming memory cells; and forming address generation circuitry coupled to the memory cells; and forming a microprocessor coupled to the memory cells and to the address generation circuitry, wherein the microprocessor is adapted to produce read requests for data stored in the memory cells; wherein each read request includes a start memory cell address; wherein, in response to a first start memory cell address from a first read request, the address generation circuitry is adapted to produce an anticipated start memory cell address in anticipation of a second read request from the microprocessor; wherein the burst access memory is adapted to provide a first data series in response to the first start memory cell address and an anticipated data series in response to the anticipated start memory cell address; and wherein the anticipated data series follows the first data series to maintain an active data output stream. - View Dependent Claims (38, 39, 40)
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Specification