Method for testing chip configuration settings
First Claim
1. A method for testing configuration space settings of a chip, comprising the steps of:
- providing a main board including a chip to be tested, the chip having a configuration space defined therein;
providing a BIOS program including a configuration space setting test process therein;
starting power for said main board;
performing a power-on self-test;
loading said BIOS program; and
executing said configuration space setting test process to verify correspondence of said configuration space defined in said chip to the configuration space settings of said chip.
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Abstract
The present invention relates to a method for testing a chip, particularly to a method for testing chip configuration settings, essentially installing the chip on a main board after the chip fabrication is finished. The test comprises starting power first of all, a power on self test being performed by the system; loading a BIOS program, wherein the BIOS program includes a configuration test process; testing the configuration settings of the chip by the configuration test process; inputting test data in turn; then enabling registers corresponding to the chip configuration space depending on the test data, for starting the chip operation; obtaining the data, produced by the chip operation, to be compared with an expected result, in order for performing the verification of chip configuration settings at the final stage before the actual chip operation is started, so as to speed the development and modification for the chip.
8 Citations
12 Claims
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1. A method for testing configuration space settings of a chip, comprising the steps of:
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providing a main board including a chip to be tested, the chip having a configuration space defined therein; providing a BIOS program including a configuration space setting test process therein; starting power for said main board; performing a power-on self-test; loading said BIOS program; and executing said configuration space setting test process to verify correspondence of said configuration space defined in said chip to the configuration space settings of said chip. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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Specification