Circuit for generating an identification code for an IC

• US 7,210,634 B2
• Filed: 02/12/2004
• Issued: 05/01/2007
• Est. Priority Date: 02/12/2004
• Status: Expired due to Fees

• Current Assignee: ICID, LLC
• Original Assignee: ICID, LLC
• Inventors: Sapiro, Stephen
• Primary Examiner(s): LEE, SEUNG H
• Application Number:
  US10/778,688
• Publication Number:
  US 20050183047A1
• Time in Patent Office: 1,174 Days
• Field of Search: 235/385, 702/73, 702/173
• US Class Current: 235/492
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06Q 20/341 Active cards, i.e. cards including their own processing means, e.g. including an IC or chip
• CPC Class Codes: G06Q 20/346 Cards serving only as information carrier of service
• CPC Class Codes: G07F 7/082 Features insuring the integrity of the data on or in the card
• CPC Class Codes: G07F 7/1008 Active credit-cards provided with means to personalise their use, e.g. with PIN-introduction/comparison system

Abstract

A ID circuit produces a unique binary identification code (ID) for each integrated circuit in which it is implemented by setting states of each bit of the ID as a function of random variations in material forming the IC that occur at the time the IC is fabricated. The ID circuit includes an ID generating circuit for generating the ID, a non-volatile memory, and a control circuit for writing the ID generated by the ID generating circuit into the non-volatile memory in response to a first occurrence of a write cue event. Thereafter the control circuit responds to each occurrence of a read cue event by reading the ID out of the non-volatile memory and providing it as an IC output.

Claims

1. An integrated circuit (IC) comprising:

an ID generating circuit for generating a binary identification code (ID) having a plurality of bits, wherein a state of each bit of the plurality of bits is determined by random process variation in material forming the IC;

a non-volatile memory; and

a control circuit for responding to a write cue event by writing the ID generated by the ID generating circuit into the non-volatile memory.

2. The IC in accordance with claim 1 wherein the control circuit also reads the ID out of the non-volatile memory and provides the ID as an output of the IC.

3. The IC in accordance with claim 2 wherein the control circuit reads the ID out of the non-volatile memory and provides the ID as an output of the IC in response to a read cue event.

4. The IC in accordance with claim 3 wherein each read cue event comprises an application of a read code as input to the IC.

5. The IC in accordance with claim 4 wherein each write cue event comprises application of a read code as input to the IC.

6. The IC in accordance with claim 5 wherein each write cue event comprises application of a write code as input to the IC.

7. The IC in accordance with claim 1 wherein the ID generating circuit comprises:

a plurality of identification cells, wherein each identification cell produces an output of state determined by random process variation in material forming the identification cell, and

a circuit for generating the ID as a function of outputs of the plurality of identification cells.

8. The IC in accordance with claim 7 wherein each identification cell comprises at least one transistor, and wherein the value of the output of that identification cell is a function of a random process variation in material forming the at least one transistor.

9. The IC in accordance with claim 8 wherein each identification cell comprises two transistors, and wherein the value of the output of that identification cell is a function of a difference random process variations in material forming the transistors.

10. The IC in accordance with claim 7 wherein each identification cell comprises at least one resistor, and wherein the value of the output of that identification cell is a function random process variation in material forming the at least one resistor.

11. The IC in accordance with claim 10 wherein each identification cell comprises two resistors, and wherein the value of the output of that identification cell is a function of a difference in random process variations in material forming the resistors.

12. The IC in accordance with claim 1 wherein the control circuit writes the ID generated by the ID generating circuit into the non-volatile memory once in response to a first occurrence of the write cue event and then refrains from writing the ID generated by the ID generating circuit into the non-volatile memory in response to subsequent occurrences of the write cue event.

13. The IEC in accordance with claim 1 wherein the control circuit writes a flag code into the non-volatile memory when it writes the ID generated by the ID generating circuit into the non-volatile memory in response to the write cue event.

14. The IC in accordance with claim 13 wherein the control circuit writes the ID generated by the ID generating circuit and a flag code into the non-volatile memory in response to a first occurrence of the write cue event, and responds to each subsequent occurrence of the write cue event by determining whether the non-volatile memory stores the flag code.

15. The IC in accordance with claim 14 wherein the write cue event comprises application of power to the control circuit.

16. The IC in accordance with claim 14 wherein the write cue event comprises application of a code as input to the IC.

17. The IC in accordance with claim 1 wherein the write cue event is application of power to the control circuit.

18. The IC in accordance with claim 1 wherein the write cue event is application of a code as input to the IC.

19. The IC in accordance with claim 1 further comprising:

an indicating circuit for generating an indicating signal indicating whether the ID resides in the non-volatile memory,

wherein when the indicating signal indicates that the ID does not reside in the non-volatile memory upon an occurrence of the write cue event, the control circuit responds to that occurrence of the write cue event by writing the ID to the non-volatile memory and then transmitting a control signal the indicating circuit to set the indicating signal to indicate that the ID resides in the non-volatile memory, and

wherein when the indicating signal indicates that the ID resides in the non-volatile memory upon an occurrence of the write cue event, the control circuit responds to that occurrence of the write cue event by refraining from writing the ID to the non-volatile memory.

20. The IC in accordance with claim 19 wherein the indicating circuit includes a fuse and responds to the control signal from the control circuit by blowing the fuse, thereby altering a state of the indicating signal.