Process and arrangement for the selective metallization of 3D structures

• US 7,211,504 B2
• Filed: 08/29/2003
• Issued: 05/01/2007
• Est. Priority Date: 09/02/2002
• Status: Expired due to Fees

• Current Assignee: Polaris Innovations Limited (Wi-LAN Inc.)
• Original Assignee: Infineon Technologies AG
• Inventors: Uhlendorf, Ingo
• Primary Examiner(s): Dang; Phuc T.
• Application Number:
  US10/652,520
• Publication Number:
  US 20040087127A1
• Time in Patent Office: 1,341 Days
• Field of Search: 438/614, 438/620, 438/622, 438/623, 438/625, 438/652, 438/665, 438/674
• US Class Current: 438/614
• CPC Class Codes: C25D 17/001 Apparatus specially adapted for electrolytic coating of wafers, e.g. semiconductors or solar cells
• CPC Class Codes: C25D 17/06 Suspending or supporting devices for articles to be coated
• CPC Class Codes: C25D 3/48 of gold
• CPC Class Codes: C25D 5/06 Brush or pad plating
• CPC Class Codes: C25D 7/123 Semiconductors first coated with a seed layer or a conductive layer
• CPC Class Codes: H01L 2224/0231 Manufacturing methods of the redistribution layers
• CPC Class Codes: H01L 2224/02331 Multilayer structure
• CPC Class Codes: H01L 2224/02381 Side view
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/05655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/11825 Plating, e.g. electroplating, electroless plating
• CPC Class Codes: H01L 2224/13008 Bump connector integrally formed with a redistribution layer on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13564 Only on the bonding interface of the bump connector
• CPC Class Codes: H01L 2224/13566 Both on and outside the bonding interface of the bump connector
• CPC Class Codes: H01L 2224/13583 Three-layer coating
• CPC Class Codes: H01L 2224/13644 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/13647 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13655 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/16227 : the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 24/11 : Manufacturing methods for bumps on insulating substrates H01L21/4853
• CPC Class Codes: H01L 24/13 : of an individual bump connector
• CPC Class Codes: H01L 24/16 : of an individual bump connector
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01005 : Boron [B]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01068 : Erbium [Er]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/014 : Solder alloys

Abstract

A process is provided for the selective metallization of 3D structures, particularly for the selective gold-plating of 3D contact structures on wafers, such as contact bumps, which are electrically connected to a bond pad on the wafer via a three-dimensional, mechanically flexible structure in the form of a redistribution layer, for subsequent electrical connection to a carrier element, e.g., a printed circuit board. The process is intended to considerably simplify the process sequence. The metallization of the previously prepared 3D structures on the wafer is carried out electrochemically, under current or potential control, by the structures being partially immersed in an electrolyte with a fixed surface. The electrolyte can be covered with a membrane which is permeable to the corresponding ions, or alternatively a gel electrolyte may be used.

Claims

1. A process for metallization of 3D structures of raised portions of circuits on a wafer that are raised relative to the wafer surface in a direction normal to the wafer surface for subsequent electrical connection to a carrier element, the process comprising the steps of:

providing an electrolyte with a fixed surface, contacting only said 3D raised circuit portions that are raised relative to the wafer surface in a direction normal to the wafer surface with said fixed surface of said electrolyte, and

applying current between said 3D raised circuit portions that are raised relative to the wafer surface in a direction normal to the wafer surface and said electrolyte to electrochemically metallize said 3D raised circuit portions selectively.

2. The process according to claim 1, characterized in that the step of contacting said raised 3D circuit portions comprises immersing said raised 3D circuit portions to a depth which is sufficient for a surface portion of the 3D structure which is to be metallized to be completely wetted.

3. The process according to claim 1 wherein the electrolyte is a gel electrolyte.

4. The process according to claim 3 wherein the gel electrolyte comprises inorganic materials.

5. The process according to claim 4 wherein the gel electrolyte comprises a silica gel.

6. The process according to claim 3 wherein the gel electrolyte comprises organic materials.

7. The process according to claim 6 wherein the gel electrolyte comprises at least one organic material selected from the group of polyacrylic acid, polyvinylphosphoric acid, polyethyleneamine, polyvinylamine, PRO (polyelectrolyte), polyvinylidene fluoride hexafluoropropylene, polyamidoacrylic acid and carboxyrnethyl cellulose and any combination thereof.

8. The process according to claim 1 wherein the electrolyte is covered with a membrane which is permeable to the ions of the electrolyte.

10. The process according to claim 1, characterized in that the step of contacting said raised 3D circuit portions that are raised relative to the wafer surface in a direction normal to the wafer surface comprises immersing said raised 3D circuit portions that are raised relative to the wafer surface in a direction normal to the wafer surface to a depth which is sufficient for a surface portion of the 3D structure which is to be metallized to be completely wetted.

9. A process for metallization of 3D structures of raised portions of circuits on a wafer that are raised relative to the wafer surface in a direction normal to the wafer surface for subsequent electrical connection to a carrier element, the process comprising the steps of:

providing an electrolyte with a fixed surface, contacting only said 3D raised circuit portions that are raised relative to the wafer surface in a direction normal to the wafer surface with said fixed surface of said electrolyte, and

applying current between said 3D raised circuit portions that are raised relative to the wafer surface in a direction normal to the wafer surface and said electrolyte to electrochemically metallize said 3D raised circuit portions selectively.