Production method for wiring structure of semiconductor device

• US 7,211,505 B2
• Filed: 09/21/2005
• Issued: 05/01/2007
• Est. Priority Date: 10/24/2003
• Status: Active Grant

• Current Assignee: LAPIS Semiconductor Co., Ltd. (ROHM Co., Ltd.)
• Original Assignee: OKI Electric Industry Company Limited
• Inventors: Abe, Kazuhide
• Primary Examiner(s): Picardat; Kevin M.
• Application Number:
  US11/230,525
• Publication Number:
  US 20060014380A1
• Time in Patent Office: 587 Days
• Field of Search: 438/618, 438/631, 438/633, 438/627, 438/648, 438/653, 438/687, 438/637, 438/643
• US Class Current: 438/618
• CPC Class Codes: H01L 21/2885 using an external electrical current, i.e. electro-deposition
• CPC Class Codes: H01L 21/76829 characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
• CPC Class Codes: H01L 21/76834 formation of thin insulating films on the sidewalls or on top of conductors H01L21/76831 takes precedence
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/7685 the layer covering a conductive structure H01L21/76849 takes precedence
• CPC Class Codes: H01L 21/76885 By forming conductive members before deposition of protective insulating material, e.g. pillars, studs
• CPC Class Codes: H01L 23/53238 Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
• CPC Class Codes: H01L 23/53295 Stacked insulating layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

In a wiring structure of a semiconductor device, dielectric tolerance of the wiring is improved by preventing diffusion of the wiring material. The wiring structure of the semiconductor device includes a first insulating film having plural grooves, plural wiring films formed protrusively above tops of the first insulating film among the grooves, plural barrier films formed on bottoms of the wiring films and up to a position on sides of the wiring films higher than the tops of the first insulating film; first cap films comprising metal films formed on tops of the wiring films, and a second cap film formed on at least respective sides of the first cap films and the barrier films.

Claims

1. A production method of a wiring structure of a semiconductor device comprising,

forming plural grooves on a first insulating film,

forming a barrier film on the first insulating film,

forming a wiring film on the barrier film in the grooves,

removing the wiring film and the barrier film such that the first insulating film between the grooves is exposed,

forming a first cap film comprising a metal film on the wiring film,

reducing a thickness of the first insulating film, so that the wiring film and the barrier film protrude above a top of the first insulating film, and

forming a second cap film on the first cap film.

2. The production method of the wiring structure of the semiconductor device according to claim 1 wherein the first cap film is formed by electroless plating.

3. The production method of the wiring structure of the semiconductor device according to claim 2 wherein the first cap film is a metal film containing Co or Ni as a main component.

4. The production method of the wiring structure of the semiconductor device according to claim 3 wherein the wiring film is a metal film of Cu or a metal film containing Cu as the main component.

11. The production method of the wiring structure of the semiconductor device according to claim 1 wherein the removing the wiring film and the barrier film comprising,

polishing the wiring film using the barrier film as a first stopper, and

polishing the wiring film and the barrier film using the first insulating film as a second stopper.

12. The production method of the wiring structure of the semiconductor device according to claim 11 wherein the polishing is performed such that a top of the wiring film is concaved with respect to a top of the barrier film in the step for polishing the wiring film and the barrier film.

13. The production method of the wiring structure of the semiconductor device according to claim 11 wherein the barrier film is a metal film comprising Ta_xN_y, Ta, or Ta_xSi_yN_z.

14. The production method of the wiring structure of the semiconductor device according to claim 11 wherein the barrier film is a metal film comprising Ti_xN_y or Ti_xSi_yN_z.

15. The production method of the wiring structure of the semiconductor device according to claim 11 wherein the barrier film is a metal film comprising W_xN_y or W_xSi_yN_z.

5. A production method of a wiring structure of a semiconductor device comprising:

forming plural grooves on a first insulating film,

forming a barrier film on the first insulating film,

forming a wiring film on the barrier film in the grooves,

removing the wiring film and the barrier film such that the first insulating film between the grooves is exposed,

forming a first cap film comprising a metal film on the wiring film,

reducing a thickness of the first insulating film, so that the wiring film and the barrier film protrude above a top of the first insulating film,

forming a second cap film on an entire surface of the semiconductor device including the first cap film, and

removing the second cap film between each of the grooves by performing an etching back process on the second cap film.

6. The production method of the wiring structure of the semiconductor device according to claim 5 wherein the second cap film is left only on respective sides of the first cap film and the barrier film.

7. The production method of the wiring structure of the semiconductor device according to claim 6 wherein the second cap film is an insulating film of Si_xN_y, Si_xO_yN_z, or Si_xC_y, or an insulating film containing Si_xC_y as the main component.

8. The production method of the wiring structure of the semiconductor device according to claim 6 wherein the second cap film is a metal film comprising Ta_xN_y, Ta, or Ta_xSi_yN_z.

9. The production method of the wiring structure of the semiconductor device according to claim 6 wherein the second cap film is a metal film comprising Ti_xN_y or Ti_xSi_yN_z.

10. The production method of the wiring structure of the semiconductor device according to claim 6 wherein the second cap film is a metal film comprising W_xN_y or W_xSi_yN_z.