Vertical electrical interconnections in a stack

• US 7,211,885 B2
• Filed: 03/14/2003
• Issued: 05/01/2007
• Est. Priority Date: 03/15/2000
• Status: Expired due to Fees

• Current Assignee: Thin Film Electronics ASA
• Original Assignee: Thin Film Electronics ASA
• Inventors: Carlsson, Johan, Nordal, Per-Erik, Gudesen, Hans Gude, Gustafsson, Go, Leidstad, Geirr Ivarsson
• Primary Examiner(s): Pham; Hoai
• Assistant Examiner(s): NGUYEN, DILINH P
• Application Number:
  US10/390,178
• Publication Number:
  US 20030218191A1
• Time in Patent Office: 1,509 Days
• Field of Search: 257/685, 257/686, 257/723, 257/777, 257/789, 257/773, 257/786, 257/689, 257/774, 257/784
• US Class Current: 257/686
• CPC Class Codes: H01L 2224/24051 Conformal with the semiconductor or solid-state device
• CPC Class Codes: H01L 2224/24145 the bodies being stacked
• CPC Class Codes: H01L 2224/24146 the HDI interconnect connecting to the same level of the lower semiconductor or solid-state body at which the upper semiconductor or solid-state body is mounted
• CPC Class Codes: H01L 2224/24225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/24226 the HDI interconnect connecting to the same level of the item at which the semiconductor or solid-state body is mounted, e.g. the item being planar
• CPC Class Codes: H01L 2224/25175 Parallel arrangements
• CPC Class Codes: H01L 2224/76155 Jetting means, e.g. ink jet
• CPC Class Codes: H01L 2224/82102 using jetting, e.g. ink jet
• CPC Class Codes: H01L 2225/06524 Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06551 Conductive connections on the side of the device
• CPC Class Codes: H01L 2225/06555 Geometry of the stack, e.g. form of the devices, geometry to facilitate stacking
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 24/24 of an individual high density interconnect connector
• CPC Class Codes: H01L 24/25 of a plurality of high density interconnect connectors
• CPC Class Codes: H01L 24/82 by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI] interconnection structure between a plurality of semiconductor chips H01L23/5389
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01005 Boron [B]
• CPC Class Codes: H01L 2924/01006 Carbon [C]
• CPC Class Codes: H01L 2924/01013 : Aluminum [Al]
• CPC Class Codes: H01L 2924/01015 : Phosphorus [P]
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01033 : Arsenic [As]
• CPC Class Codes: H01L 2924/01055 : Cesium [Cs]
• CPC Class Codes: H01L 2924/01057 : Lanthanum [La]
• CPC Class Codes: H01L 2924/01074 : Tungsten [W]
• CPC Class Codes: H01L 2924/01082 : Lead [Pb]
• CPC Class Codes: H01L 2924/10253 : Silicon [Si]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/30105 : Capacitance

Abstract

In a memory and/or data processing device having at least two stacked layers which are supported by a substrate or forming a sandwiched self-supporting structure, wherein the layers include memory and/or processing circuitry with mutual connections between the layers and/or to circuitry in the substrate, the layers the are mutually arranged such that contiguous layers form a staggered structure on at least one edge of the device and at least one electrical edge conductor is provided passing over the edge on one layer and down one step at a time, enabling the connection to an electrical conductor in any of the following layers in the stack. A method for manufacturing a device of this kind includes the steps for adding the layers successively, one layer at a time, such that the layers form a staggered structure, and for providing one or more layers with at least one electrical contact pad for linking to one or more interlayer edge connectors.

Claims

1. A memory and/or data processing device comprising

at least two stacked layers forming a stack with each of the layers having a thickness of 1 μ

m or less, the stack either forming a self-supporting structure or being provided on a substrate, and the stack including at least one of the layers staggered in at least one direction such that steps in the staggered layers being formed by exposed portions of the separate layers in the stack and with a step height corresponding to a thickness of respective layers,

one or more contact pads provided on each step in the staggered layers in electrical connection with memory and/or processing circuits in the respective layer, and

one or more electrical edge deposition connections provided on and extending over the step in direct contact with the step in each layer in the form of electrical conducting structures on the step and over and on an edge between the steps in each layer and deposited on a surface of the layers, the electrical edge connections contacting one or more contact pads in the layers and providing electrical connection between each layer and also between the layers and contact pads.

2. The memory and/or data processing device according to claim 1, wherein two or more contact pads in one or more layers are mutually connected by electrical conducting structures provided on the step in the respective layer.

3. The memory and/or data processing device according to claim 1, wherein the electrical edge connections are provided as continuous current paths between contact pads in at least three consecutive layers in the stack or between contact pads in at least two adjacent layers in the stack and the substrate adjacent to one of these layers.

4. The memory and/or data processing device according to claim 1, wherein the electrical edge connections are provided as a patched current path between two adjacent layers in the stack or between the substrate and the layer adjacent to the substrate.

5. The memory and/or data processing device according to claim 1, wherein the stack forms at least a part of a step pyramid structure, such that the layers have different areas.

6. The memory and/or data processing device according to claim 1, wherein the separate layers in the stack are mutually displaced, such that the staggered structure comprises at least one staggered portion where the steps form an exposed portion of an upper surface in the respective layers in the stack and at least one staggered portion where the steps form an exposed portion of a lower surface in the respective layers in the stack, one or more contact pads on each step in each case being electrically connected with conducting structures respectively provided on opposite surfaces of the layers.

7. The memory and/or data processing device according to claim 1, wherein a side edge of each layer between the steps is rounded or forms an inclined surface.

8. A memory and/or data processing device having at least two stacked layers provided in a stack, wherein the stack either forms a self-supporting structure or is provided on a substrate, and wherein the stack comprises at least one structure staggered in at least one direction, such that steps in the staggered structure are formed of the separate layers in the stack and with a step height corresponding to a thickness of respective layers, said memory and/or data processing device comprising

one or more contact pads provided on each step in the staggered structure in electrical connection with memory and/or processing circuits in the respective layer, and one or more electrical edge connections provided on and over the step in each layer in the form of electrical conducting structures on the step and over an edge between the steps in each layer and deposited on a surface of the layers, the electrical edge connections contacting one or more contact pads in the layers and providing electrical connection between each layer and also between the layers and contact pads, the stack being provided on the substrate and the stack forming at least part of an inverted step structure, such that an area of each layer increases with a distance from the substrate, and overlying layers being carried over the edges of underlying layers and resting against the substrate, overlying layers being formed with one or more staggered portions, whereby the number of steps in the staggered portion of a layer corresponds to the number of layers located therebeneath.

9. The memory and/or data processing device according to claim 8, wherein one or more contact pads are provided in the substrate where the layers rest against the substrate.