Self-coplanarity bumping shape for flip chip
First Claim
1. A flip chip semiconductor package, comprisingan integrated circuit chip having a plurality of stud bumps on contact sites at specified locations on a surface thereof, the stud bumps each having a base portion and having a stem portion that is more compliant than the base portion, the stem portion having a transverse planar top surface;
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Accused Products
Abstract
A stud bump structure for electrical interconnection between a pair of members includes a base portion, and a stem portion. The base portion is affixed to a pad or trace in one of the pair of members to be interconnected (such as an integrated circuit chip), and the stem end is configured to contact a metal pad on the other member (such as a printed circuit board) to complete the interconnect. According to the invention, the stem end is truncated to form a transverse plane, and the stem is more compliant than the base. Also, a method for forming a stud bump on a contact surface, includes forming a bump base portion on the surface, drawing out a generally conical tail from a top of the base, and truncating the tail to form a stem portion having a planar transverse top surface and having a length from the top of the base portion to the top surface. In some embodiments the tail portion, at least, of the stud bump is formed using a wire bonding tool. Also, a method for forming an interconnect between a first member and a second member of an electronic package includes providing one of the members with the stud bumps of the invention and then bringing the corresponding bumps and pads together in a bonding process, the compliance of the stems portions of the bumps accommodating the variance from coplanarity of the pad surfaces.
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Citations
9 Claims
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1. A flip chip semiconductor package, comprising
an integrated circuit chip having a plurality of stud bumps on contact sites at specified locations on a surface thereof, the stud bumps each having a base portion and having a stem portion that is more compliant than the base portion, the stem portion having a transverse planar top surface; - and
a substrate having a plurality of bonding pads at specified locations on a surface of thereof, the respective specified locations on the integrated circuit chip and the substrate corresponding, the stem portions of the stud bumps on the chip being in electrical contact with the corresponding pads on the substrate, wherein the bonding pads are noncoplanar, and the stud bump stem height is greater than the maximum range of noncoplanarity of all the pads on the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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Specification