Radiation hardened latch

• US 7,212,056 B1
• Filed: 10/12/2005
• Issued: 05/01/2007
• Est. Priority Date: 10/12/2005
• Status: Active Grant

• Current Assignee: Honeywell International Inc.
• Original Assignee: Honeywell International Inc.
• Inventors: Belov, Vladimir
• Primary Examiner(s): Wells; Kenneth B.
• Application Number:
  US11/248,690
• Publication Number:
  US 20070080733A1
• Time in Patent Office: 566 Days
• Field of Search: 327/208, 327210-212
• US Class Current: 327/210
• CPC Class Codes: H03K 3/356173 with synchronous operation

Abstract

A radiation hardened latch is presented. The radiation hardened latch uses two redundant inverter paths to duplicate an input signal. The duplicated inverter paths are coupled with a radiation hardened inverter that will only produce an inverted signal if both input signals have equivalent voltage levels. The radiation hardened inverter and its output signal produce a radiation hardened node that drives either one of the duplicated inverter paths back to an appropriate voltage level in the event of an SET. Because, the radiation hardened node and duplicated inverter paths are isolated, the latch may be optimized for factors such as signal speed and driving strength. These factors may be optimized without affecting radiation hardness. The radiation hardened latch may also be used to build more complex circuits such as a flip-flop.

Claims

1. A radiation hardened latch, comprising:

a first inverter having an output;

a second inverter having an output;

a radiation hardened inverter having an output, a first input coupled with the first inverter output, and a second input coupled with the second inverter output;

a third inverter having an input coupled with the radiation hardened inverter output and an output coupled with the first inverter output; and

a fourth inverter having an input coupled with the radiation hardened inverter output and an output coupled with the second inverter output.

2. The device as in claim 1, further comprising:

first and second clock inputs, the first clock input coupled with an enable input of the first inverter and the second clock input coupled with an enable input of the second inverter; and

first and second inverted clock inputs, the first inverted clock input coupled with an enable input of the third inverter and the second clock input coupled with an enable input of the fourth inverter.

3. The device as in claim 2, further comprising a clock buffer coupled to the first and second clock inputs and the first and second inverted clock inputs.

4. The device as in claim 3, wherein the clock buffer comprises:

a third clock input;

a fifth inverter having an input coupled with the third clock input, and an output coupled with the first inverted clock input;

a sixth inverter having an input coupled with the third clock input, and an output coupled with the second inverted clock input;

a seventh inverter having an input coupled with the output of the fifth inverter and an output coupled with the first clock input; and

an eighth inverter having an input coupled with the output of the sixth inverter and an output coupled with the second clock input.

5. The device as in claim 1, wherein the radiation hardened inverter comprises a series of stacked transistors.

6. The device as in claim 5, wherein the series of stacked transistors comprises first and second PMOS transistors and first and second NMOS transistors, each of the PMOS and NMOS transistors having a gate, a drain, and a source, and wherein the gate of the first PMOS transistor is coupled with the output of the second inverter and the gate of second NMOS transistor, the source of the second PMOS transistor is coupled with the drain of the first PMOS transistor, the drain of the second PMOS transistor is coupled with the drain of the first NMOS transistor and the output of the radiation hardened inverter, the gate of the second PMOS transistor is coupled with the gate of the first NMOS transistor and the output of the first inverter, and the drain of the second NMOS transistor is coupled with the source of the first NMOS transistor.

7. The device as in claim 2, wherein the first inverter has an inverse enable input coupled with the first inverse clock input, the second inverter has an inverse enable input coupled with the second inverse clock input, the third inverter has an inverse enable input coupled with the first clock input, and the fourth inverter has an inverse enable input coupled with the second clock input.

8. The device as in claim 1, wherein a second radiation hardened inverter has a first input coupled with the output of the first inverter and a second input coupled with the output of the second inverter.

9. A radiation hardened latch, comprising:

a first pair of inverters comprising a first inverter and a second inverter having interconnected outputs, wherein the first inverter has an enable input coupled with an inverted enable input of the second inverter and the second inverter has an enable input coupled with an inverted enable input of the first inverter;

a second pair of inverters comprising a third inverter and a fourth inverter having interconnected outputs, wherein the third inverter has an enable input coupled with an inverted enable input of the fourth inverter and the fourth inverter has an enable input coupled with an inverted enable input of third inverter; and

a radiation hardened inverter having an output, an input coupled with interconnected outputs of the first pair of inverters, and enable and inverted enable inputs coupled with the interconnected outputs of the second pair of inverters.

10. The device as in claim 9, further comprising a clock buffer coupled with the enable and inverted enable inputs of the first and third inverters.

11. The device as in claim 10, wherein the clock buffer comprises:

a clock input;

an fifth inverter having an input coupled with the clock input, and an output coupled with the inverted enable input of the first inverter;

a sixth inverter having an input coupled with the clock input, and an output coupled with the inverted enable input of the third inverter;

a seventh inverter having an input coupled with the output of the fifth inverter and an output coupled with the enable input of the first inverter; and

an eighth inverter having an input coupled with the output of the sixth inverter and an output coupled with the enable input of the third inverter.

12. The device as in claim 9, wherein the radiation hardened inverter comprises a series of stacked transistors.

13. The device as in claim 12, wherein series of stacked transistors comprises first and second PMOS transistors and first and second NMOS transistors, each of the PMOS and NMOS transistors having a gate, a drain, and a source, and wherein the gate of the first PMOS transistor is coupled with the output of the second inverter and the gate of second NMOS transistor, the source of the second PMOS transistor is coupled with the drain of the first PMOS transistor, the drain of the second PMOS transistor is coupled with the drain of the first NMOS transistor and the output of the third inverter, the gate of the second PMOS transistor is coupled with the gate of the first NMOS transistor and the output of the first inverter, and the drain of the second NMOS transistor is coupled with the source of the first NMOS transistor.

14. The device as in claim 9, wherein a two input inverter has a first input coupled with the interconnected outputs of the first pair of inverters and a second input coupled with the interconnected outputs of the second pair of inverters.

15. The device as in claim 14, wherein the two input inverter is radiation hardened.

16. The device as in claim 13, wherein a two input inverter has a first input coupled with the interconnected outputs of the first pair of inverters and a second input coupled with the interconnected outputs of the second pair of inverters.

17. A method of operating a radiation hardened latch, the method comprising:

inputting a latch input into first and second inverters;

enabling the first and second inverters at a periodic interval;

inputting an output of the first inverter into a first input of a radiation hardened inverter and inputting an output of the second inverter into a second input of the radiation hardened inverter, whereby a radiation hardened node is maintained at an output of the radiation hardened inverter;

outputting the radiation hardened node into third and fourth inverters;

enabling the third and fourth inverters at an inverse periodic interval;

combining an output of the third inverter to the output of the first inverter at a first output node;

combining an output of the fourth inverter with the output of the second inverter at a second output node; and

in the event of an SET, maintaining a voltage level at the first and second output nodes by the radiation hardened node.

18. The method of claim 17, further comprising:

inverting the first and second output nodes via a fifth inverter; and

receiving an output of the fifth inverter at a latch output.

19. The method of claim 17, wherein the periodic interval and the inverse periodic interval is determined by a clock generation circuit.

20. The method of claim 19, wherein the clock generation circuit is a clock buffer circuit, and wherein the clock buffer circuit isolates the periodic interval and the inverse periodic interval.