On-chip data grouping and alignment

• US 7,212,440 B2
• Filed: 12/30/2004
• Issued: 05/01/2007
• Est. Priority Date: 12/30/2004
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Corporation (Western Digital Corporation)
• Inventors: Gorobets, Sergey Anatolievich
• Primary Examiner(s): Phung; Anh
• Assistant Examiner(s): NGUYEN, DANG T
• Application Number:
  US11/026,549
• Publication Number:
  US 20060149890A1
• Time in Patent Office: 852 Days
• Field of Search: 365/185.11, 365/200, 365/238.5, 365/239, 365/189.04, 711/103, 711/170
• US Class Current: 365/185.11
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G11C 16/102 External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 8/12 Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

The invention describes the method for regrouping data read from multi-sector pages inside a memory chip. As a result, garbage collection operation time greatly reduces and overall system performance increases. Architectural features include the ability to selectively transfer individual data sectors of a page between on-chip registers and the ability to realign data sectors within a register.

Claims

1. A method of operating a memory system including a memory array, comprising:

reading a first multi-sector page of data from the memory array to a first data register;

selectively transferring less than all of the sectors of the first page of data from the first data register to a second data register; and

realigning sectors of the first page of data within one of said registers.

2. The method of claim 1, further comprising:

concurrently with said realigning sectors of the first page of data, transferring sectors of the first page of data off of the memory.

3. The method of claim 2, wherein the memory system includes a memory controller and said transferred sectors of the first page of data are transferred to the memory controller, the method further comprising:

performing in the controller an error detection and correction operation on said transferred sectors of the first page of data.

4. A method of operating a memory system including a memory array, comprising:

reading a first multi-sector page of data from the memory array to a first data register;

selectively transferring less than all of the sectors of the first page of data from the first data register to a second data register;

subsequent to transferring the first page of data to the second data register, reading a second multi-sector page of data from the memory array to the first register; and

selectively transferring less than all of the sectors of the second page of data from the first data register to portions of the second data register not containing data from the first page of data while maintaining said selectively transferred sectors of the first page of data in the second data register.

5. The method of claim 4, further comprising:

prior to said selectively transferring sectors of the second page of data to the second data register, realigning sectors of the first page of data within one of said registers.

6. The method of claim 4, further comprising:

concurrently writing the selectively transferred sectors of the first page of data and the selectively transferred sectors of the second page of data to the memory array.

7. A method of operating a memory system including a memory array, comprising:

accessing a first multi-sector page of data from the memory array; and

selectively transferring less than all of the sectors of the first page of data from the accessed first page to a first data register; and

realigning sectors of the first page of data within one of said registers.

8. The method of claim 7, further comprising:

concurrently with said realigning sectors of the first page of data, transferring sectors of the first page of data off of the memory.

9. The method of claim 8, wherein the memory system includes a memory controller and said transferred sectors of the first page of data are transferred to the memory controller, the method further comprising:

performing in the controller an error detection and correction operation on said transferred sectors of the first page of data.

10. A method of operating a memory system including a memory array, comprising:

accessing a first multi-sector page of data from the memory array; and

selectively transferring less than all of the sectors of the first page of data from the accessed first page to a first data register; and

transferring portions of the first page of data from the first data register to a second data register;

subsequent to transferring portions of the first page of data to the second data register,

accessing a second multi-sector page of data from the memory array; and

selectively transferring less than all of the sectors of the second page of data from the accessed second page to the first data register; and

selectively transferring portions of the second page of data from the first data register to portions of the second data register not containing data from the first page of data while maintaining said selectively transferred sectors of the first page of data in the second data register.

11. The method of claim 10, further comprising:

concurrently writing the selectively transferred sectors of the first page of data and the selectively transferred sectors of the second page of data to the memory array.

12. The method of claim 10, further comprising:

prior to transferring sectors of the second page of data to the second data register, realigning sectors of the first page of data within one of said registers.

13. A method of operating a memory system including a plurality of memories each including a memory array and first and second data registers, the method comprising:

performing a process in a first of said memories, including;

reading from the first memory'"'"'s array a multi-sector portion of a first page of data to the corresponding first data register;

selectively transferring less than all of the read sectors of the first page of data from the first data register to the corresponding second data register;

subsequent to performing said process in the first memory, moving the selectively transferred portion of the first page from the second data register of the first memory to the second data register of a second of said memories;

subsequent to said moving the selectively transferring the portion first page of data, reading from one of the first or second memory'"'"'s array a portion of a second page of data to the corresponding first data register; and

transferring at least a portion of the second page of data from the corresponding first data register to the corresponding second data register while maintaining said selectively transferred sectors of the first page of data in one of said second data registers.

14. The method of claim 13, further comprising:

concurrently with moving the selectively transferred portion of the first page, transferring sectors of the first page of data off of the memory.

15. The method of claim 14, wherein the memory system includes a memory controller and said transferred sectors of the first page of data are transferred to the memory controller, the method further comprising:

performing in the controller an error detection and correction operation on said transferred sectors of the first page of data.

16. The method of claim 13, further comprising:

concurrently writing the selectively transferred sectors of the first page of data and the selectively transferred sectors of the second page of data to the first and second memory arrays as a meta-page of data.

17. The method of claim 13, wherein each of the memories is structured as a plurality of semi-autonomous arrays, each of said semi-autonomous arrays storing a single sector of each of said pages.

18. The method of claim 13, wherein each of the memories is structured as a plurality of semi-autonomous arrays, each of said semi-autonomous arrays storing multiple sectors of each of said pages.

19. A memory system, comprising:

a memory chip including;

a memory array;

a first multi-sector register, wherein a plurality of data sectors can be transferred in parallel between the first register and the array;

a second multi-sector register, wherein data can be transferred between the second register and externally to the memory and wherein a plurality of data sectors can be transferred in parallel between the first register and the second register,

wherein the alignment of data sectors within one of the registers can be realigned.

20. The memory system of claim 19, further comprising:

a controller, wherein data can be transferred between the second register and the controller in parallel with realigning data sectors within one of the registers.

21. The memory system of either of claim 20, wherein the controller can perform an error detection and correction operation on data transferred from the memory to the controller.

22. A memory system, comprising:

a first memory including;

a memory array;

a first multi-sector register, wherein a plurality of data sectors can be transferred in parallel between the first register and the array;

a second multi-sector register, wherein data can be transferred between the second register and externally to the memory and wherein a plurality of data sectors can be transferred in parallel between the first register and the second register,

wherein individual data sectors can be selectively transferred between the first register and the second register.

23. The memory system of claim 22, wherein the alignment of data sectors within one of the registers can be realigned.

24. The memory system of claim 23, further comprising:

a controller, wherein data can be transferred between the second register and the controller in parallel with realigning data sectors within one of the registers.

25. The memory system of either of claim 24, wherein the controller can perform an error detection and correction operation on data transferred from the memory to the controller.

26. The memory system of claim 22, wherein the memory is structured as a plurality of semi-autonomous arrays, each of said semi-autonomous arrays storing a single sector of each of said pages.

27. The memory system of claim 22, wherein the memory is structured as a plurality of semi-autonomous arrays, each of said semi-autonomous arrays storing multiple sectors of each of said pages.

28. The memory system of claim 22, further comprising:

a second memory including multi-sector register, wherein said selectively transferred data can be exchanged between the second register of the first memory and the register of the second memory.

29. The memory system of claim 22, further comprising:

a second memory including;

a memory array;

a first multi-sector register, wherein a plurality of data sectors can be transferred in parallel between the first register and the array;

a second multi-sector register, wherein data can be transferred between the second register and externally to the memory and wherein a plurality of data sectors can be transferred in parallel between the first register and the second register,

wherein individual data sectors can be selectively transferred between the first register and the second register of the second memory in parallel with selectively transferring individual data sectors between the first register and the second register of the first memory.

30. A memory system, comprising

a first memory including:

a memory array;

a first multi-sector register, wherein a plurality of data sectors can be transferred in parallel between the first register and the array, wherein individual data sectors can be selectively transferred between the memory array and the first register; and

a second multi-sector register, wherein data can be transferred between the second register and externally to the memory and wherein a plurality of data sectors can be transferred in parallel between the first register and the second register,

wherein the alignment of data sectors within one of the registers can be realigned.

31. The memory system of claim 30, further comprising:

a controller, wherein data can be transferred between the second register and the controller in parallel with realigning data sectors within one of the registers.

32. The memory system of either of claim 31, wherein the controller can perform an error detection and correction operation on data transferred from the memory to the controller.

33. A memory system, comprising:

a first memory including;

a memory array;

a first multi-sector register, wherein a plurality of data sectors can be transferred in parallel between the first register and the array, wherein individual data sectors can be selectively transferred between the memory array and the first register; and

a second multi-sector register, wherein data can be transferred between the second register and externally to the memory and wherein a plurality of data sectors can be transferred in parallel between the first register and the second register; and

a second memory including multi-sector register, wherein said selectively transferred data can be exchanged between the second register of the first memory and the register of the second memory.