Method and apparatus for multiple context and high reliability operation of programmable logic devices

• US 7,212,448 B1
• Filed: 07/19/2005
• Issued: 05/01/2007
• Est. Priority Date: 07/19/2005
• Status: Active Grant

• Current Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Original Assignee: Xilinx, Inc. (Advanced Micro Devices, Inc.)
• Inventors: Trimberger, Stephen M.
• Primary Examiner(s): Tan; Vibol
• Application Number:
  US11/184,498
• Time in Patent Office: 651 Days
• Field of Search: 326/38, 326/39, 365/189.02, 365/230.02, 365/230.09
• US Class Current: 365/189.02
• CPC Class Codes: G06F 11/187 Voting techniques
• CPC Class Codes: G11C 29/74 using duplex memories, i.e. using dual copies
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 19/17756 for partial configuration or partial reconfiguration
• CPC Class Codes: H03K 19/1776 for memories
• CPC Class Codes: H03K 19/17764 for reliability

Abstract

A method and apparatus to provide triple modular redundancy (TMR) in one mode of operation, while providing multiple context selection during a second mode of operation. Intelligent voting circuitry facilitates both modes of operation, while further enhancing the robustness of the design when used in a TMR mode of operation. Various addressing schemes are provided, which allow dual use of the configuration data lines as selection signals using one addressing scheme, while allowing for dual use of the configuration address lines as selection signals using the second addressing scheme.

Claims

1. An integrated circuit (IC), comprising:

a plurality of reconfigurable logic resources;

a plurality of memory cells programmably coupled to the plurality of reconfigurable logic resources and adapted to configure the reconfigurable logic resources to perform logic functions in response to receiving configuration data to be stored within the memory cells; and

a plurality of selection circuits coupled to receive a mode select signal and adapted to couple a set of memory cells to the plurality of reconfigurable logic resources in response to the mode select signal,

wherein the set of memory cells is selected from a plurality of sets of memory cells configured to have the same configuration data in response to a first state of the mode select signal, and

wherein the set of memory cells is selected from the plurality of sets of memory cells configured to have different configuration data in response to a second state of the mode select signal.

2. The IC of claim 1, wherein each set of the plurality of sets of memory cells is grouped to be configured by a single data word.

3. The IC of claim 2, wherein the single data word comprises a data line for each bit of each memory cell in the plurality of sets of memory cells.

4. The IC of claim 1, wherein each set of the plurality of sets of memory cells is individually configured by corresponding single data words.

5. The IC of claim 1, wherein each selection circuit comprises:

a voting circuit coupled to receive a logic value contained within one memory cell of each set of memory cells and adapted to compare the logic values to provide a selected value to an output of the voting circuit, wherein the selected value is the same logic value as a majority of the logic values compared; and

a multiplexer coupled to receive the logic value contained within one memory cell of each set of memory cells and further coupled to receive the selected value, the multiplexer adapted to provide the selected value in response to the first state of the mode select signal and adapted to provide the logic value of the memory cell contained within the selected set in response to the second state of the mode select signal.

6. The IC of claim 5, wherein each selection circuit further comprises a latch coupled to receive an output of the multiplexer and coupled to provide a logic value received from the multiplexer to a control point of the IC.

7. The IC of claim 1, wherein each selection circuit comprises:

a first multiplexer coupled to receive a logic value from a memory cell of a first set of memory cells and further coupled to receive a logic value from a memory cell of a third set of memory cells;

a second multiplexer coupled to receive a logic value from a memory cell of a second set of memory cells and further coupled to receive the logic value from the memory cell of the first set of memory cells; and

a third multiplexer coupled to receive the logic value from the memory cell of the third set of memory cells and further coupled to receive the logic value from the memory cell of the second set of memory cells.

8. The IC of claim 7, wherein the first multiplexer is further coupled to receive a select signal, the select signal being the logic value from the memory cell of the third set of memory cells.

9. The IC of claim 7, wherein the second multiplexer is further coupled to receive a select signal, the select signal being the logic value from the memory cell of the first set of memory cells.

10. The IC of claim 7, wherein the third multiplexer is further coupled to receive a select signal, the select signal being the logic value from the memory cell of the second set of memory cells.

11. The IC of claim 7, wherein each selection circuit further comprises a voting circuit coupled to the first, second, and third multiplexers and adapted to select an output from one of the multiplexers in accordance with a majority rule.

12. The IC of claim 11, wherein the selection circuit further comprises a latch coupled to receive an output of the voting circuit and coupled to provide a logic value received from the voting circuit to a control point of the IC.

13. A method of operating a programmable logic device, comprising:

allocating multiple configuration arrays;

programming each configuration array with identical configuration data in a first mode of operation;

programming each configuration array with different configuration data in a second mode of operation;

selecting one of the identically configured configuration arrays in accordance with a majority rule during the first mode of operation; and

selecting one of the differently configured configuration arrays in accordance with a multiple context rule during the second mode of operation.

14. The method of claim 13, wherein programming each configuration array with identical configuration data comprises:

allocating a data word with configuration data;

selecting a plurality of adjacent addresses within the configuration array; and

writing the data word to each address selected.

15. The method of claim 13, wherein programming each configuration array with different configuration data comprises:

selecting a plurality of non-adjacent addresses within the configuration array; and

writing a different data word to the selected addresses.

16. The method of claim 13, wherein selecting one of the identically configured configuration arrays comprises:

receiving vote signals indicative of first, second, and third copies of the identical configuration data into a voting control circuit; and

selecting a value indicated by a majority of the vote signals.

17. The method of claim 13, wherein selecting one of the differently configured configuration arrays comprises:

receiving vote signals indicative of first, second, and third configuration contexts into a voting control circuit;

forcing the voting control circuit to select a current configuration context by setting two of the vote signals to be equal, the two vote signals being indicative of the current configuration context;

setting the third vote signal to indicate a desired configuration context; and

forcing the voting control circuit to select the desired configuration context by resetting one of the two equal vote signals to be equal to the third vote signal.

18. A method of configuring a programmable logic device (PLD), comprising:

allocating a configuration memory array within the PLD;

generating multiple configuration data sets, each configuration data set containing multiple configuration data frames;

writing each configuration data frame of a single configuration data set into discontinuous address locations of the configuration memory array when each of the multiple configuration data sets are different; and

writing each configuration data frame of a single configuration data set into continuous address locations of the configuration memory array when each of the multiple configuration data sets are equal.

19. The method of claim 18, further comprising selecting one of the configuration data sets to program reconfigurable logic resources within the PLD to perform a logic function in accordance with one context selected from a plurality of differently programmed contexts.

20. The method of claim 18, further comprising selecting one of the configuration data sets to program reconfigurable logic resources within the PLD to perform a logic function in accordance with one context selected from a plurality of equivalently programmed contexts.