Line amplifier to supplement line driver in an integrated circuit

• US 7,212,460 B1
• Filed: 12/05/2005
• Issued: 05/01/2007
• Est. Priority Date: 12/05/2005
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jung, Chulmin, Raad, George
• Primary Examiner(s): DINH, SON T
• Application Number:
  US11/294,729
• Time in Patent Office: 512 Days
• Field of Search: 365/207, 365/208, 365/226, 365/189.05
• US Class Current: 365/207
• CPC Class Codes: G11C 11/4074 Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
• CPC Class Codes: G11C 11/4091 Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
• CPC Class Codes: G11C 2207/065 Sense amplifier drivers
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals
• CPC Class Codes: G11C 7/08 Control thereof

Abstract

A method and circuitry for boosting a driven signal along a circuit line so as to reduce RC delays is disclosed. In one embodiment, the circuitry includes a line amplifier positioned at a distance from the circuitry that drives signals onto the line, for example, across a memory array. The line amplifier detects the driven signal on the line at early stages, and even before the signal reaches its full potential, the amplifier amplifies that signal and drives it back to the line to help boost the detected signal. In a preferred embodiment, the amplifier comprises a differential amplifier capable of boosting one of two input signal lines. In an alternative embodiment, the amplifier output may additionally input to a feedback loop, which loop ultimately drives a pull-up transistor to boost the detected signal and passes it back to the line to even further assist the differential amplifier in boosting. Use of the disclosed circuitry benefits, as one example, the boosting of a DRAM column select line that passes a long distance through the memory array.

Claims

1. A method for boosting a signal along a signal line in an integrated circuit, comprising:

driving the signal to a potential at a first end of the signal line via a driver circuit;

detecting the signal at a second end of the signal line via an amplifier, the amplifier having an input and an output;

boosting the detected signal on the line via the amplifier circuit; and

further boosting the detected signal on the line via a feedback loop, wherein the feedback loop receives the output of the amplifier and passes a power supply voltage to the signal line.

2. The method of claim 1, wherein the amplifier comprises a differential amplifier.

3. The method of claim 2, wherein the differential amplifier comprises a cross-coupled PMOS pair and a NMOS pass device with gate reference control.

4. The method of claim 1, further comprising at least one inverter intervening between the amplifier output and the pull up input.

5. The method of claim 1, wherein the signal line comprises a column select line.

6. The method of claim 1, wherein the signal line transgresses a memory array.

7. The method of claim 1, wherein the pull up comprises a P-channel transistor.

8. A method for boosting a signal along a signal line in an integrated circuit memory device, comprising:

driving the signal on the signal line to a potential at a first end of a memory array via a driver circuit, the signal line for enabling communication between bit lines in the memory array and a data path;

detecting the signal on the signal line at a second end of the memory array via an amplifier, the amplifier having an input and an output; and

boosting the detected signal on the signal line via the amplifier circuit.

9. The method of claim 8, further comprising further boosting the detected signal on the line via a feedback loop, wherein the feedback loop receives the output of the amplifier and passes a power supply voltage to the signal line.

10. The method of claim 8, wherein the amplifier comprises a differential amplifier.

11. The method of claim 10, wherein the differential amplifier comprises a cross-coupled PMOS pair and a NMOS pass device with gate reference control.

12. The method of claim 9, wherein the feedback loop comprises a pull up for passing a power supply voltage to the signal line.

13. The method of claim 8, wherein enabling communication between bit lines in the memory array and a data path comprises enabling a plurality of I/O circuits along the signal line.

14. Circuitry for driving a signal along a signal line in an integrated circuit, comprising:

a signal line having a first end and a second end;

a driver circuit coupled to the first end of the signal line for driving the signal on the signal line;

an amplifier having an input and an output, the amplifier input coupled to the second end of the signal line, the amplifier for detecting the driven signal and for amplifying the signal on the line; and

a pull up having an input, the pull up input coupled to the amplifier output, the pull up for passing a power supply voltage to the signal line when the amplifier amplifies the signal on the line.

15. The circuitry of claim 14, wherein the amplifier comprises a differential amplifier.

16. The circuitry of claim 15, wherein the differential amplifier comprises a cross-coupled PMOS pair and a NMOS pass device with gate reference control.

17. The circuitry of claim 14, further comprising at least one inverter intervening between the amplifier output and the pull up input.

18. The circuitry of claim 14, wherein the signal line comprises a column select line.

19. The circuitry of claim 14, wherein the signal line transgresses a memory array.

20. The circuitry of claim 14, wherein the pull up comprises a P-channel transistor.

21. Circuitry for driving a signal along a signal line in an integrated circuit, comprising:

a signal line having a first end and a second end;

a driver circuit coupled to the first end of the signal line for driving the signal on the signal line;

an amplifier having an input and an output, the amplifier input coupled to the second end of the signal line, the amplifier for detecting the driven signal and for amplifying the signal on the line; and

a feedback loop having an input, the feedback loop input coupled to the amplifier output, the feedback loop for further amplifying the signal on the signal line when the amplifier amplifies the signal on the line.

22. The circuitry of claim 21, wherein the amplifier comprises a differential amplifier.

23. The circuitry of claim 22, wherein the differential amplifier comprises a cross-coupled PMOS pair and a NMOS pass device with gate reference control.

24. The circuitry of claim 21, wherein the signal line comprises a column select line.

25. The circuitry of claim 21, wherein the signal line transgresses a memory array.

26. The circuitry of claim 21, wherein the feedback loop comprises a P-channel pull up transistor.

27. Circuitry for driving signals along first and second signal lines in an integrated circuit, comprising:

a first signal line and a second signal line;

a first driver circuit coupled to the first signal line for driving a first signal on the first signal line, and a second driver circuit for driving a second signal on the second signal line, wherein only one of the first and second signal lines are driven at a given time;

an amplifier having first and second inputs and first and second outputs, the first amplifier input coupled to the first signal line, the second amplifier input coupled to the second signal line, the amplifier for detecting the driven signal on either the first or second signal lines and for amplifying the signal on the driven signal line; and

first and second pull ups each having an input, the first pull up input coupled to the first amplifier output, the second pull up input coupled to the second amplifier output, the first and second pull ups for passing a power supply voltage respectively to either of the first and second signal lines when the amplifier amplifies the signal on the driven signal line.

28. The circuitry of claim 27, wherein the amplifier comprises a differential amplifier.

29. The circuitry of claim 28, wherein the differential amplifier comprises a cross-coupled PMOS pair and a NMOS pass device with gate reference control.

30. The circuitry of claim 27, further comprising at least one inverter intervening between the first amplifier output and the first pull up input, and at least one inverter intervening between the second amplifier output and the second pull up input.

31. The circuitry of claim 27, wherein the first and second signal lines comprise column select lines.

32. The circuitry of claim 27, wherein the first and second signal lines transgresses a memory array.

33. The circuitry of claim 27, wherein the pull up comprises a P-channel transistor.

34. Circuitry for driving signals along first and second signal lines in an integrated circuit, comprising:

a first signal line and a second signal line;

a first driver circuit coupled to the first signal line for driving a first signal on the first signal line, and a second driver circuit for driving a second signal on the second signal line, wherein only one of the first and second signal lines are driven at a given time;

an amplifier having first and second inputs and first and second outputs, the first amplifier input coupled to the first signal line, the second amplifier input coupled to the second signal line, the amplifier for detecting the driven signal on either the first or second signal lines and for amplifying the signal on the driven signal line; and

first and second feedback loops each having an input, the first feedback loop input coupled to the first amplifier output, the second feedback loop coupled to the second amplifier output, the first and second feedback loops for amplifying a signal on either of the first and second signal lines when the amplifier amplifies the signal on the driven signal line.

35. The circuitry of claim 34, wherein the amplifier comprises a differential amplifier.

36. The circuitry of claim 35, wherein the differential amplifier comprises a cross-coupled PMOS pair and a NMOS pass device with gate reference control.

37. The circuitry of claim 34, wherein the first and second signal lines comprise column select lines.

38. The circuitry of claim 34, wherein the first and second signal lines transgresses a memory array.

39. The circuitry of claim 34, wherein the first and second feedback loops comprise P-channel pull up transistors.

40. An integrated circuit memory device, comprising:

a signal line having a first end and a second end terminating at an end of a memory array, the signal line for enabling communication between bit lines in the memory array and a data path;

a driver circuit coupled to the first end of the signal line for driving the signal on the signal line; and

an amplifier having an input and an output, the amplifier input coupled to the second end of the signal line, the amplifier for detecting the driven signal and for amplifying the signal on the line.

41. The device of claim 40, further comprising a feedback loop having an input, the feedback loop input coupled to the amplifier output, the feedback loop for further amplifying the signal on the signal line when the amplifier amplifies the signal on the signal line.

42. The device of claim 41, wherein the feedback loop comprises pull up, and wherein further amplifying the signal comprises passing a power supply onto the signal line via the pull up.

43. The device of claim 40, wherein enabling communication between bit lines in the memory array and a data path comprises enabling a plurality of I/O circuits along the signal line.

44. The device of claim 40, wherein the amplifier comprises a differential amplifier.

45. The device of claim 44, wherein the differential amplifier comprises a cross-coupled PMOS pair and a NMOS pass device with gate reference control.

46. An integrated circuit memory device, comprising:

a first signal line and a second signal line each having a first end and a second end terminating at an end of a memory array, the first and second signal lines for enabling communication between bit lines in the memory array and a data path;

first and second driver circuits coupled respectively to the first ends of the first and second signal lines for driving the first and second signal lines, wherein only one of the first and second signal lines are driven at a given time; and

an amplifier having a two inputs and a two outputs, a first amplifier input coupled to the second end of the first signal line, a second amplifier input coupled to the second end of the second signal line, the amplifier for detecting the driven signal and for amplifying the signal on the driven signal line.

47. The device of claim 46, further comprising a first and second feedback loops each having an input, the first feedback loop input coupled to a first amplifier output, the second feedback loop input coupled to a second amplifier output, the first and second feedback loops for further amplifying the signal on either the first or second signal line when the amplifier amplifies the signal on the driven signal line.

48. The device of claim 47, wherein the first and second feedback loops comprises pull ups, and wherein further amplifying comprises passing a power supply onto the driven signal line via the pull up.

49. The device of claim 46, wherein enabling communication between bit lines in the memory array and a data path comprises enabling a plurality of I/O circuits along the signal line.

50. The device of claim 46, wherein the amplifier comprises a differential amplifier.

51. The device of claim 50, wherein the differential amplifier comprises a cross-coupled PMOS pair and a NMOS pass device with gate reference control.