Optimized buffer loading for packet header processing
First Claim
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1. A packet header processing engine comprising:
- an input memory configured to store incoming packet header information of a packet;
a packet processing unit configured to generate packet header information for the packet by operating on the packet header information stored in the input memory, the packet processing unit including a first processing component configured to generate layer 2 (L2) packet header information for the and a second processing component implemented in parallel with the first processing component and configured to generate layer 3 (L3) packet header information for the packet; and
a build component configured to receive the generated packet header information while the input memory stores incoming packet header information for a next packet.
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Abstract
A packet header processing engine includes a level 2 (L2) header generation unit and a level 3 (L3) header generation unit. The L2 and L3 header generation units are implemented in parallel with one another. The L2 generation unit writes L2 header information to a first buffer and the L3 generation unit writes L3 header information to a second buffer. When the L2 and L3 header generation units finish processing a packet, the packet may be unloaded from the first and second buffer while a new packet is simultaneously loaded to the packet header processing engine.
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Citations
25 Claims
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1. A packet header processing engine comprising:
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an input memory configured to store incoming packet header information of a packet; a packet processing unit configured to generate packet header information for the packet by operating on the packet header information stored in the input memory, the packet processing unit including a first processing component configured to generate layer 2 (L2) packet header information for the and a second processing component implemented in parallel with the first processing component and configured to generate layer 3 (L3) packet header information for the packet; and a build component configured to receive the generated packet header information while the input memory stores incoming packet header information for a next packet. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A method comprising:
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receiving packet header information for a packet; generating, by a first packet processing unit, layer 2 (L2) protocol information for the packet based on the received packet header information and simultaneously generating, by a second packet processing unit, layer 3 (L3) protocol information for the packet based on the received packet header information; receiving the L2 and L3 protocol information simultaneously while receiving packet header information for a next packet; writing the generated L2 protocol information for the packet to a first buffer as the L2 protocol information is generated; and writing the generated L3 protocol information for the packet to a second buffer as the L3 protocol information is generated. - View Dependent Claims (10, 11, 12)
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13. A network device for processing packets comprising:
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a buffer configured to store the packets, including header data and payload data for the packets; a descriptor reader component coupled to the buffer, the descriptor reader component receiving the header data for the packets stored in the buffer and looking up descriptor information relating to the received packet header data; and a packet header processing component coupled to the descriptor reader component, the packet header processing component receiving the packet header data and the descriptor information from the descriptor reader component, the packet header processing component additionally including an input memory configured to store incoming packet header data and descriptor information of a packet, a packet processing unit configured to generate, based on the packet header data and the descriptor information of the packet stored in the input memory, packet header data relating to a packet header protocol, the packet header processing unit including a first processing component configured to generate layer 2 (L2) packet header data for the packet, and a second processing component implemented in parallel with the first processing component and configured to generate layer 3 (L3) packet header data for the packet, and a build component configured to receive the generated L2 and L3 packet header data while the input memory stores incoming packet header information for a next packet. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20, 21, 22, 23)
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24. A device comprising:
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means for receiving packet header information; means for generating layer 2 (L2) protocol information for the packet based on the received packet header information; means for writing the generated L2 protocol information for the packet as the L2 protocol information is generated; means for generating layer 3 (L3) protocol information for the packet based on the received packet header information, the means for generating the L2 protocol information and the means for generating the L3 protocol information being implemented in parallel with one another; means for writing the generated (L3) protocol information for the packet as the L3 protocol information is generated; and means for unloading the written L2 and L3 protocol information while the means for receiving is receiving packet header information for a next packet. - View Dependent Claims (25)
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Specification