Memory hub and method for providing memory sequencing hints
First Claim
Patent Images
1. A computer system, comprising:
- a central processing unit (“
CPU”
);
a system controller coupled to the CPU, the system controller having an input port and an output port;
an input device coupled to the CPU through the system controller;
an output device coupled to the CPU through the system controller;
a storage device coupled to the CPU through the system controller;
a plurality of memory modules, each of the memory modules comprising;
a plurality of memory devices; and
a memory hub coupled to the system controller and the memory devices, the memory hub comprising;
a link interface receiving memory requests from the system controller for access to memory cells in at least one of the memory devices, at least some of the memory requests including respective memory hints providing information about the subsequent operation of the memory devices;
a memory device interface coupled to the memory devices and to the link interface, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and
a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability of the memory devices responsive to the memory hint.
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Abstract
A memory module includes a memory hub coupled to several memory devices. The memory hub is also coupled to receive a memory packet from a system controller containing a memory hint indicative of the subsequent operation of the memory devices. The memory module uses the hint to adjust the operation of the memory module, such as the number of pages to remain open or cache lines to be fetched.
268 Citations
10 Claims
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1. A computer system, comprising:
-
a central processing unit (“
CPU”
);a system controller coupled to the CPU, the system controller having an input port and an output port; an input device coupled to the CPU through the system controller; an output device coupled to the CPU through the system controller; a storage device coupled to the CPU through the system controller; a plurality of memory modules, each of the memory modules comprising; a plurality of memory devices; and a memory hub coupled to the system controller and the memory devices, the memory hub comprising; a link interface receiving memory requests from the system controller for access to memory cells in at least one of the memory devices, at least some of the memory requests including respective memory hints providing information about the subsequent operation of the memory devices; a memory device interface coupled to the memory devices and to the link interface, the memory device interface being operable to couple memory requests to the memory devices for access to memory cells in at least one of the memory devices and to receive read data responsive to at least some of the memory requests; and a memory sequencer coupled to the link interface and the memory device interface, the memory sequencer being operable to couple memory requests to the memory device interface responsive to memory requests received from the link interface, the memory sequencer further being operable to dynamically adjust operability of the memory devices responsive to the memory hint. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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Specification
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Current AssigneeRound Rock Research LLC
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Original AssigneeMicron Technology, Inc.
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InventorsJeddeloh, Joseph M.
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Primary Examiner(s)SHIN, CHRISTOPHER B
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Application NumberUS10/812,950Publication NumberTime in Patent Office1,128 DaysField of Search710 5- 7, 710 15- 19, 710/29, 710 33- 35, 710 36- 39, 710/74, 711154-160, 711/169, 711/137, 711144-146, 712233-240US Class Current710/5CPC Class CodesG06F 12/0215 with look ahead addressing ...G06F 13/1684 using multiple busesG06F 13/1694 Configuration of memory con...
