Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches
First Claim
1. A method comprising:
- assigning a first memory to a first memory channel;
assigning a second memory to a second memory channel;
the first memory being equal in memory size to the second memory;
assigning a third memory to a third memory channel;
the third memory comprising a first memory portion being equal in memory size to the first memory and comprising a second memory portion;
interleaving the first memory, the second memory and the first memory portion of the third memory in a three-way interleaving;
determining a selected memory channel from the first memory channel, the second memory channel and the third memory channel for a program address; and
mapping said program address to a physical address within said selected memory channel.
1 Assignment
0 Petitions
Accused Products
Abstract
Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.
-
Citations
22 Claims
-
1. A method comprising:
-
assigning a first memory to a first memory channel; assigning a second memory to a second memory channel;
the first memory being equal in memory size to the second memory;assigning a third memory to a third memory channel;
the third memory comprising a first memory portion being equal in memory size to the first memory and comprising a second memory portion;interleaving the first memory, the second memory and the first memory portion of the third memory in a three-way interleaving; determining a selected memory channel from the first memory channel, the second memory channel and the third memory channel for a program address; and mapping said program address to a physical address within said selected memory channel. - View Dependent Claims (2, 3, 4, 5, 6, 13, 14, 15, 16, 17)
-
-
7. A system comprising
a network processor; - and
a plurality of memory channels in communication with said network processor, the plurality of memory channels comprising a first memory channel access a first memory, a second memory channel accessing a second memory and a third memory channel accessing a third memory, the first memory being equal in memory size to the second memory, the third memory comprising a first memory portion being equal in memory size to the first memory and comprising a second memory portion, wherein the first memory, the second memory and the first memory portion of the third memory are configured to be interleaved in a three-way interleaving. - View Dependent Claims (8, 9)
- and
-
10. An article comprising:
a storage medium having stored thereon instructions that when executed by a machine result in the following; assigning a first memory to a first memory channel; assigning a second memory to a second memory channel;
the first memory being equal in memory size to the second memory;assigning a third memory to a third memory channel;
the third memory comprising a first memory portion being equal in memory size to the first memory and comprising a second memory portion;interleaving the first memory, the second memory and the first memory portion of the third memory in a three-way interleaving; determining a selected memory channel from the first memory channel, the second memory channel and the third memory channel for a program address; and mapping said program address to a physical address within said selected memory channel. - View Dependent Claims (11, 12, 18, 19, 20, 21, 22)
Specification