Method and apparatus utilizing non-uniformly distributed DRAM configurations and to detect in-range memory address matches

• US 7,213,099 B2
• Filed: 12/30/2003
• Issued: 05/01/2007
• Est. Priority Date: 12/30/2003
• Status: Expired due to Fees

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Guilford, James D., Chandra, Prashant R., Kuo, Chen-Chi, Lakshmanamurthy, Sridhar, Natarajan, Rohit, Liu, Kin-Yip
• Primary Examiner(s): Bataille; Pierre
• Assistant Examiner(s): SCHLIE, PAUL W
• Application Number:
  US10/751,263
• Publication Number:
  US 20050144413A1
• Time in Patent Office: 1,218 Days
• Field of Search: 711/5, 711/151, 711/217, 711/220, 711/170, 711/209
• US Class Current: 711/5
• CPC Class Codes: G06F 13/4243 with synchronous protocol

Abstract

Methods, software and systems to determine channel ownership and physical block location within the channel in non-uniformly distributed DRAM configurations and also to detect in-range memory address matches are presented. A first method, which may also be implemented in software and/or hardware, allocates memory non-uniformly between a number of memory channels, determines a selected memory channel from the memory channels for a program address, and maps the program address to a physical address within the selected memory channel. A second method, which may also be implemented in software and/or hardware, designates a range of memory to perform address matching, monitors memory accesses and when a memory access occurs with the specified range, perform a particular function.

Claims

1. A method comprising:

assigning a first memory to a first memory channel;

assigning a second memory to a second memory channel;

the first memory being equal in memory size to the second memory;

assigning a third memory to a third memory channel;

the third memory comprising a first memory portion being equal in memory size to the first memory and comprising a second memory portion;

interleaving the first memory, the second memory and the first memory portion of the third memory in a three-way interleaving;

determining a selected memory channel from the first memory channel, the second memory channel and the third memory channel for a program address; and

mapping said program address to a physical address within said selected memory channel.

2. The method of claim 1 wherein said determining a selected memory channel comprises:

determining whether the program address accesses an interleaved portion of memory and when said program memory address does access an interleaved portion of memory then performing an operation on said program address to obtain a memory channel number and when said program memory address does not access an interleaved portion of memory then selecting the memory channel containing non-interleaved memory.

3. The method of claim 2 wherein said determining whether the program address accesses an interleaved portion of memory comprises determining whether the program address accesses a lower three/fourths of memory.

4. The method of claim 2 wherein said performing an operation on said program address comprises performing summing modulo three arithmetic on at least a portion of said program address to obtain a remainder, said remainder comprising the memory channel number.

5. The method of claim 1 wherein said mapping said program address to a physical address comprises:

determining whether the program address accesses an interleaved portion of memory and when said program memory address does access the interleaved portion of memory then performing address interleaving of said program address and when said program memory address does not access the interleaved portion of memory then subtracting a predetermined value from said program address to obtain a physical address in the selected memory channel.

6. The method of claim 1 wherein said interleaving comprises:

determining the number of consecutive bits of a predetermined portion of the program address bits that are ones;

right shifting program address bits by a predetermined number of bits to obtain a shifted address;

adding a predetermined offset value to the shifted address to obtain an interim physical address; and

appending a predetermined number of program address bits to said interim physical address to obtain a physical address within said selected memory channel.

13. The method of claim 1 further comprising:

designating a range of addresses defined as the memory between an upper address to perform range checking and a lower address to perform range checking;

monitoring memory accesses; and

determining if any of said memory accesses occur within said range of addresses and in response to a memory access occurring with said range of memory addresses then performing a predetermined operation.

14. The method of claim 13 wherein said performing a predetermined operation comprises performing an operation selected from the group consisting of interrupting the core processor, aborting the pending memory operation, executing a halt, and sending an exception.

15. The method of claim 13 wherein said determining if any of said memory accesses occur within said range of addresses comprises determining at least one of the group consisting of determining if the starting address of the memory access lies between said upper address and said lower address, determining if the ending address of the memory access lies between said upper address and said lower address, and determining if the lower address lies between the starting address of the memory access and the ending address of the memory access.

16. The method of claim 13 wherein said upper address and said lower address are located in different blocks of memory.

17. The method of claim 13 wherein said starting address of a memory access and an ending address of the memory access are located in different blocks of memory.

7. A system comprising

a network processor;

and

a plurality of memory channels in communication with said network processor, the plurality of memory channels comprising a first memory channel access a first memory, a second memory channel accessing a second memory and a third memory channel accessing a third memory, the first memory being equal in memory size to the second memory, the third memory comprising a first memory portion being equal in memory size to the first memory and comprising a second memory portion,

wherein the first memory, the second memory and the first memory portion of the third memory are configured to be interleaved in a three-way interleaving.

8. The system of claim 7 wherein said network processor determines a memory channel for a memory access by determining whether said memory access is to an interleaved portion of memory and if the access is to an interleaved portion then performing an operation on said program address and when said program memory address does not access an interleaved portion of memory then selecting the memory channel containing non-interleaved memory.

9. The system of claim 7 wherein said network processor maps said program address to a physical address by determining whether the program address accesses an interleaved portion of memory and when said program memory address does access the interleaved portion of memory then performing address interleaving of said program address and when said program memory address does not access the interleaved portion of memory then subtracting a predetermined value from said program address to obtain a physical address in the selected memory channel.

10. An article comprising:

a storage medium having stored thereon instructions that when executed by a machine result in the following;

assigning a first memory to a first memory channel;

assigning a second memory to a second memory channel;

the first memory being equal in memory size to the second memory;

assigning a third memory to a third memory channel;

the third memory comprising a first memory portion being equal in memory size to the first memory and comprising a second memory portion;

interleaving the first memory, the second memory and the first memory portion of the third memory in a three-way interleaving;

determining a selected memory channel from the first memory channel, the second memory channel and the third memory channel for a program address; and

mapping said program address to a physical address within said selected memory channel.

11. The article of claim 10 wherein said determining a selected memory channel comprises:

determining whether the program address accesses an interleaved portion of memory and when said program memory address does access an interleaved portion of memory then performing an operation on said program address to obtain a memory channel number and when said program memory address does not access an interleaved portion of memory then selecting the memory channel containing non-interleaved memory.

12. The article of claim 10 wherein said mapping said program address to a physical address comprises:

determining whether the program address accesses an interleaved portion of memory and when said program memory address does access the interleaved portion of memory then performing address interleaving of said program address and when said program memory address does not access the interleaved portion of memory then subtracting a predetermined value from said program address to obtain a physical address in the selected memory channel.

18. The article of claim 10 wherein said instructions that when executed by a machine further result in the following:

designating a range of addresses defined as the memory between an upper address to perform range checking and a lower address to perform range checking; and

monitoring memory accesses and determining if any of said memory accesses occur within said range of addresses and in response to a memory access occurring with said range of memory addresses then performing a predetermined operation.

19. The article of claim 18 wherein said performing a predetermined operation comprises performing an operation selected from the group consisting of interrupting the core processor, aborting the pending memory operation, executing a halt, and sending an exception.

20. The article of claim 18 wherein said determining if any of said memory accesses occur within said range of addresses comprises determining at least one of the group consisting of determining if the starting address of the memory access lies between said upper address and said lower address, determining if the ending address of the memory access lies between said upper address and said lower address, and determining if the lower address lies between the starting address of the memory access and the ending address of the memory access.

21. The article of claim 18 wherein said upper address and said lower address are located in different blocks of memory.

22. The article of claim 18 wherein said starting address of a memory access and an ending address of the memory access are located in different blocks of memory.