Programmable processor and method for partitioned group element selection operation

• US 7,213,131 B2
• Filed: 01/15/2004
• Issued: 05/01/2007
• Est. Priority Date: 08/16/1995
• Status: Expired due to Fees

• Current Assignee: Microunity Systems Engineering Incorporated
• Original Assignee: Microunity Systems Engineering Incorporated
• Inventors: Moussouris, John, Hansen, Craig
• Primary Examiner(s): Coleman; Eric
• Application Number:
  US10/757,524
• Publication Number:
  US 20040205323A1
• Time in Patent Office: 1,202 Days
• Field of Search: 712/220, 712/224, 712/225, 712/226
• US Class Current: 712/220
• CPC Class Codes: G06F 15/7832 on one IC chip (single chip microprocessors)
• CPC Class Codes: G06F 9/30014 with variable precision
• CPC Class Codes: G06F 9/30018 Bit or string instructions
• CPC Class Codes: G06F 9/30025 Format conversion instructions, e.g. Floating-Point to Integer, decimal conversion
• CPC Class Codes: G06F 9/30029 Logical and Boolean instructions, e.g. XOR, NOT
• CPC Class Codes: G06F 9/30032 Movement instructions, e.g. MOVE, SHIFT, ROTATE, SHUFFLE
• CPC Class Codes: G06F 9/30036 Instructions to perform operations on packed data, e.g. vector, tile or matrix operations
• CPC Class Codes: G06F 9/3004 to perform operations on memory
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30054 Unconditional branch instructions
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30109 having multiple operands in a single register
• CPC Class Codes: G06F 9/30112 comprising data of variable length
• CPC Class Codes: G06F 9/3012 Organisation of register space, e.g. banked or distributed register file
• CPC Class Codes: G06F 9/30123 according to context, e.g. thread buffers
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3016 Decoding the operand specifier, e.g. specifier format
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/3816 Instruction alignment, e.g. cache line crossing
• CPC Class Codes: G06F 9/3824 : Operand accessing
• CPC Class Codes: G06F 9/383 : Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3851 : from multiple instruction streams, e.g. multistreaming
• CPC Class Codes: G06F 9/3861 : Recovery, e.g. branch miss-prediction, exception handling error detection or correction G06F11/00
• CPC Class Codes: G06F 9/3873 : Variable length pipelines, e.g. elastic pipeline
• CPC Class Codes: G06F 9/3885 : using a plurality of independent parallel functional units

Abstract

A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

Claims

1. A programmable processor comprising:

an instruction path;

a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

a register file operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a first and a second register each having a register width, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width of the first and second registers, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

2. The processor of claim 1 wherein each field of the data selection operand provides a sufficient number of bits to specify any one of the plurality of data elements.

3. The processor of claim 2 wherein each field of the data selection operand has a width of n bits wherein the plurality of data elements comprises 2ⁿ data elements.

4. The processor of claim 1 wherein the data selection operand is provided by a register specified by the single instruction.

5. The processor of claim 4 wherein the data selection operand has a width equal to the specified register width.

6. The processor of claim 1 wherein the catenated result is provided to a register.

7. The processor of claim 1 wherein the plurality of data elements has a combined width equal to the width of the first register plus the width of the second register.

8. The processor of claim 1 wherein the instruction further specifies a data element width of the plurality of data elements.

9. The processor of claim 1 wherein each data element has a width of 8 bits.

10. The processor of claim 1 wherein the catenated result has a width of 128 bits.

11. The processor of claim 1 wherein for each field of the data selection operand, a relative location of the field within the data selection operand corresponds to a relative location of the predetermined position within the catenated result.

12. The processor of claim 1 wherein the execution unit is further operable to, in response to decoding a second single instruction specifying a third and a fourth register each containing a plurality of operands, multiply the plurality of floating point operands in the third register by the plurality of operands in the fourth register to produce a plurality of products and provide the plurality of products to partitioned fields of a result register as a second catenated result.

13. A programmable processor comprising:

an instruction path;

a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

a register file operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a register having a register width, the register providing a plurality of data elements each having an elemental width smaller than the register width of the register, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

14. A data processing system comprising:

(a) a bus coupling components in the data processing system;

(b) an external memory coupled to the bus;

(c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising;

an instruction path;

a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

a register file operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a first and a second register each having a register width, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width of the first and second registers, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

15. The system of claim 14 wherein each field of the data selection operand provides a sufficient number of bits to specify any one of the plurality of data elements.

16. The system of claim 15 wherein each field of the data selection operand has a width of n bits wherein the plurality of data elements comprises 2ⁿ data elements.

17. The system of claim 14 wherein the data selection operand is provided by a register specified by the single instruction.

18. The system of claim 17 wherein the data selection operand has a width equal to the specified register width.

19. The system of claim 14 wherein the catenated result is provided to a register.

20. The system of claim 14 wherein the plurality of data elements has a combined width equal to the width of the first register plus the width of the second register.

21. The system of claim 14 wherein the instruction further specifies a data element width of the plurality of data elements.

22. The system of claim 14 wherein each data element has a width of 8 bits.

23. The system of claim 14 wherein the catenated result has a width of 128 bits.

24. The system of claim 14 wherein for each field of the data selection operand, a relative location of the field within the data selection operand corresponds to a relative location of the predetermined position within the catenated result.

25. The system of claim 14 wherein the execution unit is further operable to, in response to decoding a second single instruction specifying a third and a fourth register each containing a plurality of operands, multiply the plurality of floating point operands in the third register by the plurality of operands in the fourth register to produce a plurality of products and provide the plurality of products to partitioned fields of a result register as a second catenated result.

26. A data processing system comprising:

(a) a bus coupling components in the data processing system;

(b) an external memory coupled to the bus;

(c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising;

an instruction path;

a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

a register file operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a register having a register width, the register providing a plurality of data elements each having an elemental width smaller than the register width of the register, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.

27. A programmable processor comprising:

an instruction path;

a data path;

a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a plurality of registers storing a plurality of 8-bit data elements, an index register storing an index vector comprising a plurality of equal-sized selectors stored in partitioned fields of the index register and a destination register, the execution unit is operable to, for each selector in the index vector, provide a data element selected by the selector to a predetermined position in the destination register.

28. The programmable processor set forth in claim 27 wherein the plurality of registers comprises two registers.

29. The programmable processor set forth in claim 27 wherein the plurality of registers comprises tow 64-bit registers storing a combined total of sixteen 8-bit data elements.

30. The programmable processor set forth in claim 27 wherein the number of selectors stored in the index register is equal to the number of predetermined positions in the destination register.

31. The programmable processor set forth in claim 27 wherein the index register is a 64-bit register.

32. The programmable processor set forth in claim 27 wherein the index vector comprises n equal-sized selectors and the destination register comprises n equal-sized predetermined positions.

33. The programmable processor set forth in claim 32 wherein the selector stored in a lowest order set of bits of the index register provides a data element to a lowest order set of bits of the Destination register, the selector in a second lowest order set of bits of the index register provide a data element to a second lowest order set of bits of the destination register and the selector stored in a highest order set of bits of the index register provides a data element to a highest order set of bits of the destination register.

34. The programmable processor set forth in claim 27 wherein the destination register is a 128-bit register.

35. The programmable processor set forth in claim 27 wherein each of the equal-sized selectors stored in partitioned fields of the index register is a 4-bit selector.

36. The programmable processor set forth in claim 27 wherein the index register stores sixteen 4-bit selectors.

37. A programmable processor comprising:

an instruction path;

a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

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a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a first register storing a first plurality of 8-bit data elements, a second register storing a second plurality of 8-bit data elements, an index register storing an index vector comprising a plurality of equal-sized selectors stored in partitioned fields of the index register and a destination register, the execution unit is operable to, for each selector in the index vector, provide a data element from one of the first or second plurality of 8-bit data elements selected by the selector to a predetermined 8-bit position in the destination register, wherein the predetermined positions are contiguous blocks of bits that take up an entire width of the destination register.

38. The programmable processor set forth in claim 37 wherein the first and second registers are 64-bit registers, the index register is a 64-bit register and each selector stored in the index register has a sufficient number of bits to select anyone of the 8-bit data elements in the first or second pluralities of 8-bit data elements.

39. The programmable processor set forth in claim 37 wherein the destination register is a 128-bit register.

40. The programmable processor set forth in claim 37 wherein each of the equal-sized selectors stored in partitioned fields of the index register is a 4-bit selector.

41. A device having installed therein a programmable processor, the programmable processor comprising:

an instruction path;

a data path;

a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction path and data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a plurality of registers storing a plurality of 8-bit data elements, an index register storing an index vector comprising a plurality of equal-sized selectors stored in partitioned fields of the index register and a destination register, the execution unit is operable to, for each selector in the index vector, provide a data element selected by the selector to a predetermined position in the destination register.

42. The device set forth in claim 41 wherein the plurality of registers comprises two registers.

43. The device set forth in claim 41 wherein the plurality of registers comprises two 64-bit registers storing a combined total of sixteen 8-bit data elements.

44. The device set forth in claim 41 wherein the number of selectors stored in the index register is equal to the number of predetermined positions in the destination register.

45. The device set forth in claim 41 wherein the index register is a 64-bit register.

46. The device set forth in claim 41 wherein the index vector comprises n equal-sized selectors and the destination register comprises n equal-sized predetermined positions.

47. The device set forth in claim 46 wherein the selector stored in a lowest order set of bits of the index register provides a data element to a lowest order set of bits of the Destination register, the selector in a second lowest order set of bits of the index register provide a data element to a second lowest order set of bits of the destination register and the selector stored in a highest order set of bits of the index register provides a data element to a highest order set of bits of the destination register.

48. The device set forth in claim 41 wherein the destination register is a 128-bit register.

49. The device set forth in claim 41 wherein each of the equal-sized selectors stored in partitioned fields of the index register is a 4-bit selector.

50. The device set forth in claim 41 wherein the index register stores sixteen 4-bit selectors.

51. A device having installed therein a programmable processor, the programmable processor comprising:

an instruction path;

a data path;

an external interface operable to receive data from an external source and communicate the received data over the data path;

a cache operable to retain data communicated between the external interface and the data path;

a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; and

an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a first register storing a first plurality of 8-bit data elements, a second register storing a second plurality of 8-bit data elements, an index register storing an index vector comprising a plurality of equal-sized selectors stored in partitioned fields of the index register and a destination register, the execution unit is operable to, for each selector in the index vector, provide a data element from one of the first or second plurality of 8-bit data elements selected by the selector to a predetermined 8-bit position in the destination register, wherein the predetermined positions are contiguous blocks of bits that take up an entire width of the destination register.

52. The device set forth in claim 51 wherein the first and second registers are 64-bit registers, the index register is a 64-bit register and each selector stored in the index register has a sufficient number of bits to select anyone of the 8-bit data elements in the first or second pluralities of 8-bit data elements.

53. The device set forth in claim 51 wherein the destination register is a 128-bit register.

54. The device set forth in claim 51 wherein each of the equal-sized selectors stored in partitioned fields of the index register is a 4-bit selector.