Programmable processor and method for partitioned group element selection operation
DCFirst Claim
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1. A programmable processor comprising:
- an instruction path;
a data path;
an external interface operable to receive data from an external source and communicate the received data over the data path;
a cache operable to retain data communicated between the external interface and the data path;
a register file operable to receive and store data from the data path and communicate the stored data to the data path; and
an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a first and a second register each having a register width, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width of the first and second registers, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.
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Abstract
A programmable processor and method for improving the performance of processors by incorporating an execution unit operable to decode and execute single instructions specifying a data selection operand and a first and a second register providing a plurality of data elements, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.
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Citations
54 Claims
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1. A programmable processor comprising:
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an instruction path; a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a cache operable to retain data communicated between the external interface and the data path; a register file operable to receive and store data from the data path and communicate the stored data to the data path; and an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a first and a second register each having a register width, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width of the first and second registers, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12)
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13. A programmable processor comprising:
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an instruction path; a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a cache operable to retain data communicated between the external interface and the data path; a register file operable to receive and store data from the data path and communicate the stored data to the data path; and an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a register having a register width, the register providing a plurality of data elements each having an elemental width smaller than the register width of the register, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.
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14. A data processing system comprising:
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(a) a bus coupling components in the data processing system; (b) an external memory coupled to the bus; (c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising; an instruction path; a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a cache operable to retain data communicated between the external interface and the data path; a register file operable to receive and store data from the data path and communicate the stored data to the data path; and an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a first and a second register each having a register width, the first and second registers providing a plurality of data elements each having an elemental width smaller than the register width of the first and second registers, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result. - View Dependent Claims (15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25)
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26. A data processing system comprising:
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(a) a bus coupling components in the data processing system; (b) an external memory coupled to the bus; (c) a programmable microprocessor coupled to the bus and capable of operation independent of another host processor, the microprocessor comprising; an instruction path; a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a cache operable to retain data communicated between the external interface and the data path; a register file operable to receive and store data from the data path and communicate the stored data to the data path; and an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a data selection operand and a register having a register width, the register providing a plurality of data elements each having an elemental width smaller than the register width of the register, the data selection operand comprising a plurality of fields each selecting one of the plurality of data elements, the execution unit is operable to provide the data element selected by each field of the data selection operand to a predetermined position in a catenated result.
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27. A programmable processor comprising:
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an instruction path; a data path; a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; and an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a plurality of registers storing a plurality of 8-bit data elements, an index register storing an index vector comprising a plurality of equal-sized selectors stored in partitioned fields of the index register and a destination register, the execution unit is operable to, for each selector in the index vector, provide a data element selected by the selector to a predetermined position in the destination register. - View Dependent Claims (28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A programmable processor comprising:
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an instruction path; a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a cache operable to retain data communicated between the external interface and the data path;
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a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; andan execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a first register storing a first plurality of 8-bit data elements, a second register storing a second plurality of 8-bit data elements, an index register storing an index vector comprising a plurality of equal-sized selectors stored in partitioned fields of the index register and a destination register, the execution unit is operable to, for each selector in the index vector, provide a data element from one of the first or second plurality of 8-bit data elements selected by the selector to a predetermined 8-bit position in the destination register, wherein the predetermined positions are contiguous blocks of bits that take up an entire width of the destination register. - View Dependent Claims (38, 39, 40)
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41. A device having installed therein a programmable processor, the programmable processor comprising:
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an instruction path; a data path; a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; and an execution unit coupled to the instruction path and data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a plurality of registers storing a plurality of 8-bit data elements, an index register storing an index vector comprising a plurality of equal-sized selectors stored in partitioned fields of the index register and a destination register, the execution unit is operable to, for each selector in the index vector, provide a data element selected by the selector to a predetermined position in the destination register. - View Dependent Claims (42, 43, 44, 45, 46, 47, 48, 49, 50)
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51. A device having installed therein a programmable processor, the programmable processor comprising:
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an instruction path; a data path; an external interface operable to receive data from an external source and communicate the received data over the data path; a cache operable to retain data communicated between the external interface and the data path; a plurality of registers operable to receive and store data from the data path and communicate the stored data to the data path; and an execution unit coupled to the instruction path and the data path and operable to decode and execute instructions received from the instruction path, wherein in response to decoding a single instruction specifying a first register storing a first plurality of 8-bit data elements, a second register storing a second plurality of 8-bit data elements, an index register storing an index vector comprising a plurality of equal-sized selectors stored in partitioned fields of the index register and a destination register, the execution unit is operable to, for each selector in the index vector, provide a data element from one of the first or second plurality of 8-bit data elements selected by the selector to a predetermined 8-bit position in the destination register, wherein the predetermined positions are contiguous blocks of bits that take up an entire width of the destination register. - View Dependent Claims (52, 53, 54)
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Specification