Layout data saving method, layout data converting device and graphic verifying device

• US 7,213,217 B2
• Filed: 08/04/2005
• Issued: 05/01/2007
• Est. Priority Date: 08/06/2002
• Status: Expired due to Fees

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Technology Corporation (Renesas Electronics Corporation)
• Inventors: Kamon, Kazuya
• Primary Examiner(s): Chiang; Jack
• Assistant Examiner(s): TAT, BINH C
• Application Number:
  US11/196,393
• Publication Number:
  US 20050268270A1
• Time in Patent Office: 635 Days
• Field of Search: 716 2- 4, 716 8- 11
• US Class Current: 716/103
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

There are saved layout data which have parent cell information indicative of higher order cell data to directly refer to low order cell data (or basic element data), thereby defining a reverse hierarchical structure. More specifically, both of basic element data (figD1 and figD2) have cell data (cell2) as the parent cell information, all of basic element data (figD3 to figD5) have cell data (cell3) as the parent cell information, the cell data (cell3) have two identical cell data (cell2 and cell2) as the parent cell information, and the cell data (cell2) have three identical cell data (cell3, cell3 and cell3) as the parent cell information.

Claims

1. A layout data converting device configured to convert first type layout data into second type layout data,

comprising:

a hierarchical structure analyzing section configured to analyze said hierarchical structure based on said child cell information of said first type layout data; and

a reverse hierarchical structure generating section configured to add said parent cell information to each of said plurality of basic element data and said plurality of cell data, respectively, to generate said second type layout data based on a result of analysis carried out by said hierarchical structure analyzing section, wherein

said first type and second type layout data having a plurality of basic element data, each of which directly defines a graphic to be a layout pattern of a component of a semiconductor device and a plurality of cell data constructed by a hierarchical structure such that reference is finally made to said basic element data, respectively,

each of said plurality of said cell data in said first type layout data having child cell information indicative of low order cell data or said basic element data to which reference is directly made, thereby defining said hierarchical structure in a positive direction, and

each of said plurality of said basic element data and said plurality of cell data in said second type layout data having parent cell information indicative of high order cell data to which reference is directly made, thereby defining said hierarchical structure in a reverse direction.

2. A layout data converting device configured to convert second type layout data into first type layout data,

comprising:

a reverse hierarchical structure analyzing section configured to analyze said hierarchical structure based on said parent cell information of said second type layout data; and

a hierarchical structure generating section configured to add said child cell information to each of said plurality of cell data, respectively, to generate said first type layout data based on a result of analysis carried out by said reverse hierarchical structure analyzing section, wherein

said first type and second type layout data having a plurality of basic element data, each of which directly defines a graphic to be a layout pattern of a component of a semiconductor device and a plurality of cell data constructed by a hierarchical structure such that reference is finally made to said basic element data,

each of said plurality of said cell data in said first type layout data having child cell information indicative of low order cell data or said basic element data to which reference is directly made, thereby defining said hierarchical structure in a positive direction, and

each of said plurality of said basic element data and said plurality of cell data in said second type layout data having parent cell information indicative of high order cell data to which reference is directly made, thereby defining said hierarchical structure in a reverse direction.

3. A graphic verifying device configured to carry out a graphic verification processing based on layout data,

comprising:

a reverse hierarchical structure analyzing section configured to analyze said hierarchical structure based on said parent cell information of said layout data; and

a graphic verifying section configured to carry out a verification processing based on an occupied region on an actual space region of a graphic defined by said plurality of basic element data on the basis of a result of analysis performed by said hierarchical structure analyzing section, wherein said layout data having a plurality of basic element data, each of which directly defines a graphic to be a layout pattern of a component of a semiconductor device and a plurality of cell data constructed by a hierarchical structure such that reference is

finally made to said basic element data, each of said plurality of basic element data and said plurality of cell data having parent cell information to be information about high order cell data to which reference is directly made, thereby defining said hierarchical structure in a reverse direction.

4. The graphic verifying device according to claim 3, wherein

said actual space region is constituted by a plurality of mesh regions, and

said graphic verifying section includes an occupation rate calculating section configured to occupy an occupation rate in each of said plurality of mesh regions of a graphic defined by said plurality of basic element data.

5. The graphic verifying device according to claim 3, wherein

said actual space region comprises a plurality of mesh regions, and

said graphic verifying section comprises a Fourier analyzing section configured to carry out Fourier analysis in relation to an occupied region of said mesh regions of a graphic defined by said plurality of basic element data.

6. The graphic verifying device according to claim 3, wherein

said graphic verifying section is configured to execute an occupied region transformation process so as to remove an overlapping portion from an occupied region of one of two or more graphics when said graphics occupying said actual space region overlap each other on the same region.

7. The graphic verifying device according to claim 3, wherein

said graphic verifying section is configured to newly generates a graphic for subtraction in an overlapping portion when two or more graphics occupying said actual space region overlap each other on the same region.

8. The graphic verifying device according to claim 3, wherein

assuming that said layout data are second type layout data, first type layout data are received,

said first type layout data have a plurality of basic element data, each of which directly defines a graphic to be a layout pattern of a component of a semiconductor device and a plurality of cell data constructed by a hierarchical structure such that reference can be finally made to said basic element data, and

each of said plurality of cell data in said first type layout data has child cell information indicative of low order cell data or said basic element data to which reference is directly made, thereby defining said hierarchical structure in a positive direction,

said graphic verifying device further comprising:

a layout data converting section configured to receive said first type layout data, to convert said first type layout data into said second type layout data, and to output said second type layout data to said reverse hierarchical structure analyzing section.