PMOS transistor with compressive dielectric capping layer

• US 7,214,630 B1
• Filed: 05/06/2005
• Issued: 05/08/2007
• Est. Priority Date: 05/06/2005
• Status: Active Grant

• Current Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Original Assignee: Novellus Systems Incorporated (Lam Research Corporation)
• Inventors: Sims, James S., Varadarajan, Bhadri N., Singhal, Akhil
• Primary Examiner(s): Kebede; Brook
• Application Number:
  US11/124,443
• Time in Patent Office: 732 Days
• Field of Search: 438/758, 438/761, 438/778, 438/783, 438/791, 438/792, 427/563, 427/568, 427/578, 427/579
• US Class Current: 438/778
• CPC Class Codes: C23C 16/30 Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
• CPC Class Codes: C23C 16/56 After-treatment
• CPC Class Codes: H01L 21/02112 characterised by the material of the layer
• CPC Class Codes: H01L 21/02126 the material containing Si, O, and at least one of H, N, C, F, or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/02167 the material being a silicon carbide not containing oxygen, e.g. SiC, SiC:H or silicon carbonitrides H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/02205 the layer being characterised by the precursor material for deposition
• CPC Class Codes: H01L 21/02211 the compound being a silane, e.g. disilane, methylsilane or chlorosilane
• CPC Class Codes: H01L 21/02216 the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0234 treatment by exposure to a plasma
• CPC Class Codes: H01L 21/3105 After-treatment
• CPC Class Codes: H01L 21/3148 Silicon Carbide layers
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7843 the means being an applied insulating layer

Abstract

A salicide layer is deposited on the source/drain regions of a PMOS transistor. A dielectric capping layer having residual compressive stress is formed on the salicide layer by depositing a plurality of PECVD dielectric sublayers and plasma-treating each sublayer. Compressive stress from the dielectric capping layer is uniaxially transferred to the PMOS channel through the source-drain regions to create compressive strain in the PMOS channel. To form a compressive dielectric layer, a deposition reactant mixture containing A1 atoms and A2 atoms is provided in a vacuum chamber. Element A2 is more electronegative than element A1, and A1 atoms have a positive oxidation state and A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms. A deposition plasma is generated by applying HF and LF radio-frequency power to the deposition reactant mixture, and a sublayer of compressive dielectric material is deposited. A post-treatment plasma is generated by applying HF and LF radio-frequency power to a post-treatment gas that does not contain at least one of A1 atoms and A2 atoms. Compressive stress in the dielectric sublayer is increased by treating the sublayer in the post-treatment plasma. Processes of depositing a dielectric sublayer and post-treating the sublayer in plasma are repeated until a desired thickness is achieved. The resulting dielectric layer has residual compressive stress.

Claims

1. A method of fabricating a dielectric layer having compressive stress on a semiconductor substrate, comprising processes of:

(a) providing in a vacuum chamber a deposition reactant mixture comprising A1 atoms of a chemical element A1 and A2 atoms of a chemical element A2, wherein said element A2 is more electronegative than said element A1, and wherein said A1 atoms have a positive oxidation state and said A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms;

(b) applying high-frequency (HF) and low-frequency (LF) power to said deposition reactant mixture to generate a deposition plasma containing excited A1-species and excited A2-species;

(c) depositing a dielectric sublayer on said substrate using said deposition plasma;

(d) providing a post-treatment gas containing peening species to a vacuum chamber, said post-treatment gas being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms;

(e) applying HF and LF power to said post-treatment gas to generate a post-treatment plasma, said post-treatment plasma comprising excited peening species, and said post-treatment plasma being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms;

(f) post-treating said dielectric sublayer in said post-treatment plasma; and

(g) repeating said processes (c) and (f) of depositing a dielectric sublayer and post-treating said dielectric sublayer until a desired thickness of a dielectric material is achieved.

2. A method of fabricating a dielectric layer as in claim 1 wherein said processes of applying HF and LF power to said deposition reactant mixture comprises applying LF power greater than said HF power.

3. A method of fabricating a dielectric layer as in claim 1 wherein said processes of applying HF and LF power to said post-treatment gas comprises applying LF power greater than said HF power.

4. A method of fabricating a dielectric layer as in claim 1 wherein said A1 element is selected from a group consisting of silicon (Si), boron (B), and carbon (C), and said A2 element is selected from a group consisting of nitrogen (N), carbon (C), and oxygen (O).

5. A method of fabricating a dielectric layer as in claim 4 wherein said dielectric material comprises a dielectric material selected from the group consisting of silicon nitride, silicon carbide, nitrogen-doped silicon carbide, boron nitride, silicon boron nitride, boron carbide, silicon boron carbide, carbon nitride, silicon oxide, and oxygen-doped silicon carbide.

6. A method of fabricating a dielectric layer as in claim 1 wherein said processes of providing a deposition reactant mixture further comprise:

providing an inert gas in said vacuum chamber.

7. A method of fabricating a dielectric layer as in claim 1 wherein said processes of providing a deposition reactant mixture further comprise:

providing peening species in said vacuum chamber.

8. A method of fabricating a dielectric layer as in claim 1 wherein said processes of providing a deposition reactant mixture comprise:

flowing into said vacuum chamber a silicon-containing species and a nitrogen-containing species.

9. A method of fabricating a dielectric layer as in claim 8 wherein said processes of providing a deposition reactant mixture comprise:

flowing a silicon-containing species selected from the group consisting of tetramethylsilane, tetraethylsilane, and silane.

10. A method of fabricating a dielectric layer as in claim 8 wherein said processes of providing a deposition reactant mixture comprise:

flowing ammonia (NH₃) into said vacuum chamber.

11. A method of fabricating a dielectric layer as in claim 8 wherein said processes of providing a post-treatment gas containing peening species comprise:

flowing ammonia (NH₃).

12. A method of fabricating a dielectric layer as in claim 1 wherein said processes of providing a post-treatment gas containing peening species comprises:

providing a post-treatment gas containing hydrogen atoms.

13. A method of fabricating a dielectric layer as in claim 1 wherein said processes of providing a post-treatment gas containing peening species comprises:

providing a post-treatment gas containing A2 atoms and not containing A1 atoms.

14. A method of fabricating a dielectric layer as in claim 1 wherein said processes of providing a post-treatment gas containing peening species comprises:

providing a post-treatment gas containing A1 atoms and not containing A2 atoms.

15. A method of fabricating a dielectric layers as in claim 1 wherein said processes of providing a post-treatment gas further comprise:

providing an inert gas in said vacuum chamber.

16. A method of fabricating a dielectric layer as in claim 1 wherein said processes of repeating said processes (c) and (f) of depositing a dielectric sublayer and post-treating said dielectric sublayer comprise:

repeating said processes to form a plurality of dielectric sublayers on said substrate, said plurality being in a range of about from 12 to 40 dielectric sublayers.

17. A method of fabricating a dielectric layer as in claim 1 wherein said processes of post-treating said dielectric sublayer in said post-treatment plasma comprise:

exposing said dielectric sublayer to said post-treatment plasma for a sublayer post-treatment time in a range of about from 0.5 second to 10 seconds.

18. A method of fabricating a dielectric layer as in claim 1 wherein said processes of depositing a dielectric sublayer comprise:

depositing a dielectric sublayer having a thickness in a range of about from 0.5 nm to 20 nm.

19. A method of fabricating a dielectric layer having compressive stress on a semiconductor substrate, comprising processes of:

(a) providing in a vacuum chamber a deposition reactant mixture comprising A1 atoms of a chemical element A1 and A2 atoms of a chemical element A2, wherein said element A2 is more electronegative than said element A1, and wherein said A1 atoms have a positive oxidation state and said A2 atoms have a negative oxidation state when A1 atoms are bonded with A2 atoms;

(b) applying high-frequency (HF) and low-frequency (LF) power to said deposition reactant mixture to generate a deposition plasma containing excited A1-species and excited A2-species;

(c) depositing a dielectric layer on said substrate using said deposition plasma;

(d) providing a post-treatment gas containing peening species to a vacuum chamber, said post-treatment gas being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms;

(e) applying HF and LF power to said post-treatment gas to generate a post-treatment plasma, said post-treatment plasma comprising excited peening species, and said post-treatment plasma being substantially free of at least one type of atoms selected from the group consisting of A1-type atoms and A2-type atoms; and

(f) post-treating said dielectric layer in said post-treatment plasma.

20. A method of fabricating a dielectric layer as in claim 19 wherein said processes of applying HF and LF power to said deposition reactant mixture comprises applying LF power greater than said HF power.

21. A method of fabricating a dielectric layer as in claim 19 wherein said processes of applying HF and LF power to said post-treatment gas comprises applying LF power greater than said HF power.

22. A method of fabricating a dielectric layer as in claim 19 wherein said A1 element is selected from a group consisting of silicon (Si), boron (B), and carbon (C), and said A2 element is selected from a group consisting of nitrogen (N), carbon (C), and oxygen (O).

23. A method of fabricating a dielectric layer as in claim 22 wherein said dielectric material comprises a dielectric material selected from the group consisting of silicon nitride, silicon carbide, nitrogen-doped silicon carbide, boron nitride, silicon boron nitride, boron carbide, silicon boron carbide, carbon nitride, silicon oxide, and oxygen-doped silicon carbide.

24. A method of fabricating a dielectric layer as in claim 19 wherein said processes of providing a deposition reactant mixture further comprise:

providing an inert gas in said vacuum chamber.

25. A method of fabricating a dielectric layer as in claim 19 wherein said processes of providing a deposition reactant mixture further comprise:

providing peening species in said vacuum chamber.

26. A method of fabricating a dielectric layer as in claim 19 wherein said processes of providing a deposition reactant mixture comprise:

flowing into said vacuum chamber a silicon-containing species and a nitrogen-containing species.

27. A method of fabricating a dielectric layer as in claim 26 wherein said processes of providing a deposition reactant mixture comprise:

flowing a silicon-containing species selected from the group consisting of tetramethylsilane, tetraethylsilane, and silane.

28. A method of fabricating a dielectric layer as in claim 26 wherein said processes of providing a deposition reactant mixture comprise:

flowing ammonia (NH₃) into said vacuum chamber.

29. A method of fabricating a dielectric layer as in claim 26 wherein said processes of providing a post-treatment gas containing peening species comprise:

flowing ammonia (NH₃).

30. A method of fabricating a dielectric layer as in claim 19 wherein said processes of providing a post-treatment gas containing peening species comprises:

providing a post-treatment gas containing hydrogen atoms.

31. A method of fabricating a dielectric layer as in claim 19 wherein said processes of providing a post-treatment gas containing peening species comprises:

providing a post-treatment gas containing A2 atoms and not containing A1 atoms.

32. A method of fabricating a dielectric layer as in claim 19 wherein said processes of providing a post-treatment gas containing peening species comprises:

providing a post-treatment gas containing A1 atoms and not containing A2 atoms.

33. A method of fabricating a dielectric layers as in claim 19 wherein said processes of providing a post-treatment gas further comprise:

providing an inert gas in said vacuum chamber.

34. A method of fabricating a dielectric layer as in claim 19 wherein said processes of post-treating said dielectric sublayer in said post-treatment plasma comprise:

exposing said dielectric layer to said post-treatment plasma for a post-treatment time in a range of about from 0.5 second to 10 seconds.