3-D column select circuit layout in semiconductor memory devices

• US 7,214,963 B2
• Filed: 08/18/2005
• Issued: 05/08/2007
• Est. Priority Date: 12/24/2004
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Choi, Byung-Gil, Suh, Young-Ho
• Primary Examiner(s): Prenty; Mark V.
• Application Number:
  US11/206,437
• Publication Number:
  US 20060138465A1
• Time in Patent Office: 628 Days
• Field of Search: 257/67, 257/74, 257/351, 257/369, 257/393, 257/903
• US Class Current: 257/67
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H10B 10/00 Static random access memory [SRAM] devices
• CPC Class Codes: H10B 10/12 comprising a MOSFET load element
• CPC Class Codes: Y10S 257/903 FET configuration adapted for use as static memory cell

Abstract

A column select circuit in a Static Random Access Memory (SRAM) having a three-dimensional layout can include a lower CMOS layer in a substrate and an upper NMOS layer above the lower layer. An intermediate PMOS layer is located between the upper NMOS layer and the lower CMOS layer.

Claims

1. A column select circuit in a Static Random Access Memory (SRAM) having a three-dimensional layout, the column select circuit comprising:

a lower CMOS layer in a substrate;

an upper NMOS layer above the lower layer; and

an intermediate PMOS layer between the upper NMOS layer and the lower CMOS layer.

2. A circuit according to claim 1 wherein the upper NMOS layer comprises first and second separate active areas in which respective NMOS transistors are formed.

3. A circuit according to claim 2 wherein the first and second separate active areas define an opening therebetween which electrically isolates the separate active areas, the circuit further comprising:

a VDD power supply voltage line extending through the opening to the intermediate PMOS layer and electrically coupled thereto.

4. A circuit according to claim 3 wherein the intermediate PMOS layer includes first and second PMOS transistors wherein the VDD power supply voltage line is electrically coupled to respective source regions of the first and second PMOS transistors.

5. A circuit according to claim 4 wherein drain regions of the first and second PMOS transistors are electrically coupled to first and second partial bit lines.

6. A circuit according to claim 5 wherein drain regions of first and second NMOS transistors included in the separate active areas are electrically coupled to the first and second partial bit lines.

7. A circuit according to claim 4 wherein the first and second PMOS transistors comprise first and second precharge transistors.

8. A circuit according to claim 4 wherein the first and second NMOS transistors comprise first and second switching transistors configured to switch data from the SRAM to first and second partial bit lines.

9. A circuit according to claim 1 wherein the intermediate and upper layers are electrically isolated from one another.

10. A circuit according to claim 9 wherein the intermediate and upper layers comprise first and second crystallized silicon layers.

11. A column path circuit layout in a semiconductor memory device, the semiconductor memory device comprising a column path circuit for enabling one of a plurality of partial bit lines to be operatively connected to one global bit line, the column path circuit layout comprising:

a metal oxide semiconductor (MOS) layer as a first layer formed in a substrate;

a second layer over the MOS layer for forming precharge transistors; and

a third layer for forming path switching transistors, the third layer being divided and formed over the second layer other than a region through which a contact of a power line for supplying a power to the second layer passes.

12. The layout according to claim 11, wherein the second layer and the third layer are electrically isolated from each other, each being a crystallized silicon layer.

13. The layout according to claim 11, wherein the region through which the contact passes is a region through a tungsten contact plug passes without making an electrical short-circuit.

14. The layout according to claim 11, wherein the precharge transistors are P-type MOS transistors.

15. The layout according to claim 14, wherein the path switching transistors are N-type MOS transistors.

16. The layout according to claim 11, wherein the second layer and the third layer are active regions of the transistors.

17. The layout according to claim 13, wherein the tungsten contact plug electrically connects between a source of the precharge transistor and the power line.

18. The layout according to claim 11, wherein the semiconductor memory device comprises a plurality of static memory cells each having six transistors laid out in a three-dimension.

19. The layout according to claim 11, wherein the MOS layer is an N-type active region for a floating node.

20. A column path circuit layout in a semiconductor memory device, wherein:

when first and second P-type metal oxide semiconductor (MOS) transistors and first and second N-type MOS transistors constitute part of the column path circuit, the first and second P-type MOS transistors having sources connected to a power supply voltage in parallel, drains connected to first and second corresponding partial bit lines, respectively, and gates for receiving first and second column select signals, respectively, and the first and second N-type MOS transistors having drains and gates connected to the corresponding drains and gates of the first and second P-type MOS transistors, respectively, and sources connected to a global bit line in common,

the first and second P-type MOS transistors have active regions formed as a first silicon layer which is formed over an MOS layer,

the first and second N-type MOS transistors have active regions formed as a second silicon layer which is formed over the first silicon layer, and

the second silicon layer is divided into two with a boundary therebetween being a contact region formed for applying the power supply voltage to the first silicon layer.

21. The layout according to claim 20, wherein the first and second silicon layers are isolated electrically from each other, each being a crystallized silicon layer.

22. The layout according to claim 20, wherein the contact region is a region through which a tungsten contact plug passes without making an electrical short-circuit.

23. The layout according to claim 22, wherein the first and second P-type MOS transistors are transistors for precharging the partial bit lines.

24. The layout according to claim 22, wherein the first and second N-type MOS transistors are column path switching transistors connected to the global bit line.

25. The layout according to claim 24, wherein the MOS layer is an N-type active region for a floating node.

26. The layout according to claim 25, wherein the semiconductor memory device comprises a plurality of static memory cells each having six transistors laid out in a three-dimension.

27. The layout according to claim 22, wherein the tungsten contact plug electrically connects between a source of the precharge transistor and the power line.

28. A column path circuit layout in a semiconductor memory device, wherein:

when part of the column path circuit is configured by laminating and laying out first and second metal oxide semiconductor (MOS) transistors of a first conduction type and first and second MOS transistors of a second conduction type on different conductive substrate layers, the first and second MOS transistors having sources connected to a power supply voltage in parallel, drains connected to first and second corresponding partial bit lines, respectively, and gates for receiving first and second column select signals, respectively, and the first and second MOS transistors having drains and gates connected to the corresponding drains and gates of the first and second MOS transistors of the first conduction type, respectively, and sources connected to a global bit line in common,

the first and second MOS transistors of the first conductive type share one active region which is formed on the first conductive substrate layer while the first and second MOS transistors of the second conductive type are laid out in divided active regions of the second conductive substrate layer, respectively, with a boundary therebetween being a contact region for power feed.

29. The layout according to claim 28, wherein the contact region for power feed is a region through which a tungsten contact plug passes without making an electrical short-circuit.

30. The layout according to claim 28, wherein the second conductive substrate layer is a crystallized silicon layer which is insulatedly formed over the first conductive substrate layer, and an MOS layer is formed on a P-type substrate and under the first conductive substrate layer.