Multi-source, multi-gate MOS transistor with a drain region that is wider than the source regions

• US 7,214,992 B1
• Filed: 10/27/2004
• Issued: 05/08/2007
• Est. Priority Date: 10/27/2004
• Status: Active Grant

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Strachan, Andy, Brisbin, Douglas
• Primary Examiner(s): Owens; Douglas W.
• Assistant Examiner(s): ARENA, ANDREW OWENS
• Application Number:
  US10/974,145
• Time in Patent Office: 923 Days
• Field of Search: 257/327, 257/368, 257/393, 257/401, 257/E27.06
• US Class Current: 257/401
• CPC Class Codes: H01L 21/823425 manufacturing common source or drain regions between a plurality of conductor-insulator-semiconductor structures
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate

Abstract

The drain breakdown voltage walk-in of a dual-source, dual-gate PMOS transistor is significantly reduced by utilizing source regions which have a width that is equal to or less than a width of the drain region. By utilizing source regions with widths that are equal to or less than the width of the drain region, the current density in the drain region is significantly reduced which reduces the number of hot charge carriers that are trapped at the silicon-to-silicon dioxide interface which, turn in, reduces the drain breakdown voltage walk-in rate.

Claims

1. A PMOS transistor formed in a semiconductor material, the semiconductor material having a top surface and an n-type conductivity, the PMOS transistor comprising:

a first doped region of a p-type conductivity formed in the semiconductor material to contact the top surface, the first doped region having a first width and a heavy dopant concentration;

a second doped region of a p-type conductivity formed in the semiconductor material to contact the top surface, the second doped region having a second width and a heavy dopant concentration;

a third doped region of the p-type conductivity formed in the semiconductor material to contact the top surface, the third doped region having a third width, a heavy dopant concentration, and lying between the first and second doped regions, the third width being greater than the first and second widths, the first, second, and third widths being measured normal to a shortest line that extends from the first doped region to the third doped region;

a fourth doped region of the p-type conductivity formed in the semiconductor material to contact the top surface, the fourth doped region having a light dopant concentration and surrounding the third doped region at the top surface;

a first channel region of the semiconductor material that lies between the first and third doped regions;

a second channel region of the semiconductor material that lies between the second and third doped regions;

a first insulation region formed on the semiconductor material over the first channel region;

a second insulation region formed on the semiconductor material over the second channel region;

a first gate formed on the first insulation layer over the first channel region;

a second gate formed on the second insulation layer over the second channel region;

an isolation region, the isolation region being formed adjacent to, and spaced apart from, two sides of the third doped region, and contacting the first and second channels regions, and the first and second doped regions; and

a fifth doped region of the p-type conductivity, the fifth doped region contacting the first doped region and the isolation region and having a dopant concentration that is less than the first doped region.

2. The PMOS transistor of claim 1 wherein the third doped region only receives holes.

3. The PMOS transistor of claim 1 wherein the first and second gates are electrically connected together, and the first and second doped regions are electrically connected together.

4. A transistor formed in a semiconductor material, the semiconductor material having a top surface and a first conductivity type, the transistor comprising:

a first doped region of a second conductivity type that contacts the top surface of the semiconductor material, the first doped region having a number of sides, a first width, and only a heavily-doped region;

a second doped region of the second conductivity type that contacts the top surface of the semiconductor material, the second doped region having a number of sides, a second width, and only a heavily-doped region;

a third doped region of the second conductivity type that contacts the top surface of the semiconductor material, the third doped region lying between the first and second doped regions, and having a number of sides, a third width, a lightly-doped region, and a heavily-doped region;

a first channel region that lies between and contacts the first and third doped regions;

a second channel region that lies between and contacts the second and third doped regions;

a first insulation region that contacts the top surface of the semiconductor material over the first channel region;

a second insulation region that contacts the top surface of the semiconductor material over the second channel region;

a first gate that contacts the first insulation layer over the first channel region;

a second gate that contacts the second insulation layer over the second channel region;

a fourth doped region of the second conductivity type that contacts the top surface of the semiconductor material, the fourth doped region being lightly-doped and contacting the first doped region; and

a fifth doped region of the second conductivity type that contacts the top surface of the semiconductor material, the fourth and fifth doped regions being spaced apart, the fifth doped region being lightly-doped and contacting the first doped region, the first, fourth, and fifth doped regions having a combined width that is substantially equal to the third width, the combined width and the third width being measured normal to a shortest line that extends from the first doped region to the third doped region.

5. The transistor of claim 4 wherein the first width is less than the third width, the first and third widths being measured normal to said shortest line that extends from the first doped region to the third doped region.

6. The transistor of claim 5 wherein the first width is less than a width of the heavily-doped region of the third doped region, the width of the heavily-doped region of the third doped region being measured normal to said shortest line.

7. The transistor of claim 4 and further comprising an isolation region that surrounds the first, second, and third doped regions at the top surface, the isolation region contacting only one side of the first doped region, and no portion of the heavily-doped region of the third doped region.

8. The transistor of claim 7 wherein the isolation region contacts only one side of the second doped region.

9. A transistor formed in a semiconductor material, the semiconductor material having a top surface and a first conductivity type, the transistor comprising:

a first doped region of a second conductivity type that contacts the top surface of the semiconductor material, the first doped region having a number of sides, a first width, and only a heavily-doped region;

a second doped region of the second conductivity type that contacts the top surface of the semiconductor material, the second doped region having a number of sides, a second width, and only a heavily-doped region;

a third doped region of the second conductivity type that contacts the top surface of the semiconductor material, the third doped region lying between the first and second doped regions, and having a number of sides, a third width, a lightly-doped region, and a heavily-doped region, the first width being less than the third width, the first and third widths being measured normal to a shortest line that extends from the first doped region to the third doped region, the first width being equal to a width of the heavily-doped region of the third doped region, the width of the heavily-doped region of the third doped region being measured normal to said shortest line;

a first channel region that lies between and contacts the first and third doped regions;

a second channel region that lies between and contacts the second and third doped regions;

a first insulation region that contacts the top surface of the semiconductor material over the first channel region;

a second insulation region that contacts the top surface of the semiconductor material over the second channel region;

a first gate that contacts the first insulation layer over the first channel region; and

a second gate that contacts the second insulation layer over the second channel region.

10. A transistor formed in a semiconductor material, the semiconductor material having a top surface and a first conductivity type, the transistor comprising:

a first doped region of a second conductivity type that contacts the top surface of the semiconductor material, the first doped region having a first width and only a heavily-doped region;

a second doped region of the second conductivity type that contacts the top surface of the semiconductor material, the second doped region having a second width and only a heavily-doped region;

a third doped region of the second conductivity type that contacts the top surface of the semiconductor material, the third doped region lying between the first and second doped regions, and having a third width, a lightly-doped region, and a heavily-doped region, the first width being less than the third width, the first and third widths being measured normal to a shortest line that extends from the first doped region to the third doped region, the first width being equal to a width of the heavily-doped region of the third doped region, the width of the heavily-doped region of the third doped region being measured normal to said shortest line;

a first channel region that lies between and contacts the first and third doped regions;

a second channel region that lies between and contacts the second and third doped regions;

a first insulation region that contacts the top surface of the semiconductor material over the first channel region;

a second insulation region that contacts the top surface of the semiconductor material over the second channel region;

a first gate that contacts the first insulation layer over the first channel region; and

a second gate that contacts the second insulation layer over the second channel region.