Flip chip in leaded molded package and method of manufacture thereof

• US 7,215,011 B2
• Filed: 08/25/2005
• Issued: 05/08/2007
• Est. Priority Date: 12/16/1999
• Status: Expired due to Term

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Joshi, Rajeev, Tangpuz, Consuelo N., Manatad, Romel N.
• Primary Examiner(s): Andujar, Leonardo
• Assistant Examiner(s): SODERHOLM, KRISTA Z
• Application Number:
  US11/213,182
• Publication Number:
  US 20050280126A1
• Time in Patent Office: 621 Days
• Field of Search: 257/666, 257/680, 257/288, 257/350, 257/684, 257/673
• US Class Current: 257/673
• CPC Class Codes: H01L 2223/54406 comprising alphanumeric information
• CPC Class Codes: H01L 2223/54433 containing identification or tracking information
• CPC Class Codes: H01L 2223/54486 Located on package parts, e.g. encapsulation, leads, package substrate
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3185 the coating covering also the sidewalls of the semiconductor body
• CPC Class Codes: H01L 23/49531 the additional leads being a wiring board
• CPC Class Codes: H01L 23/49562 for devices being provided for in H01L29/00
• CPC Class Codes: H01L 23/544 Marks applied to semiconductor devices or parts, e.g. registration marks, alignment structures, wafer maps test patterns for characterising or monitoring manufacturing processes H01L22/00
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/13091 Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]

Abstract

A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Claims

1. A semiconductor die package comprising:

a leadframe;

a die that includes a backside, wherein the backside of the die forms a first electrical terminal;

solder coupling a frontside of the die to the leadframe, wherein the frontside of the die comprises a second electrical terminal, and wherein the first electrical terminal and the second electrical terminal are terminals in a MOSFET device; and

a body including an encapsulating material that encapsulates the die such that the backside of the die is adjacent to a window defined within the body, wherein the leadframe has leads and wherein ends of the leads of the leadframe are substantially coplanar with the backside of the die.

2. The package of claim 1 wherein the solder comprises solder bumps.

3. The package of claim 1 further comprising a marking on the body on a surface opposite the window.

4. The package of claim 3 wherein the marking is a laser marking.

5. The package of claim 3 wherein the marking includes ink.

6. The package of claim 1 wherein the leadframe comprises preplated leads.

7. The package of claim 1 wherein the leadframe comprises preformed leads.

8. The package of claim 1 wherein the leadframe comprises preplated leads and preformed leads.

9. The package of claim 1 wherein the die is coupled to the leadframe via solder bumps, and wherein the solder bumps have been re-flowed.

10. The package of claim 1 wherein the die is a first die and wherein the package includes a second die coupled to the leadframe on the opposite side as the first die.

11. A semiconductor die package comprising:

a leadframe;

a semiconductor die that includes a backside including a first electrical terminal and a frontside including a second electrical terminal, wherein the first electrical terminal and the second electrical terminal are terminals in an electrical device, wherein the semiconductor die is mounted on the leadframe; and

a body comprising an encapsulating material encapsulating the semiconductor die and at least a portion of the leadframe, wherein the body has a window and an exterior surface, wherein the backside of the semiconductor die is exposed through the window of the body and wherein the backside is substantially flush with the exterior surface of the body.

12. The package of claim 11 wherein the electrical device is a power transistor.

13. The package of claim 11 further comprising:

a second semiconductor die including a second backside mounted on the leadframe, wherein the second backside is exposed through a second window in the body.

14. The package of claim 11 further comprising solder between the die and the leadframe.

15. The package of claim 11 wherein the second electrical terminal is a source terminal or gate terminal at the frontside.

16. The package of claim 11 wherein the leadframe is pre-plated.

17. The package of claim 11 wherein the leadframe includes leads and wherein ends of the leads are co-planar with the backside of the semiconductor die.

18. The package of claim 11 wherein the backside of the semiconductor die is metallized.

19. The package of claim 11 wherein the device is a MOSFET, and wherein the backside forms a drain terminal of the MOSFET in the die.

20. The semiconductor die package of claim 11 wherein the leadframe includes only leads that extend laterally away and outward from the body, and wherein surfaces of the leads are substantially coplanar with the backside of the die.