Switched operation amplifier

• US 7,215,160 B2
• Filed: 09/28/2005
• Issued: 05/08/2007
• Est. Priority Date: 09/29/2004
• Status: Expired due to Fees

• Current Assignee: Tian Holdings LLC (Intellectual Ventures LLC)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Liu, Chih-Min
• Primary Examiner(s): Tra; Quan
• Assistant Examiner(s): Aranda; Rey
• Application Number:
  US11/236,673
• Publication Number:
  US 20060066360A1
• Time in Patent Office: 587 Days
• Field of Search: 327/91, 327/94, 327560-563, 330/9, 330/253
• US Class Current: 327/94
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H03F 3/005 using switched capacitors, e.g. dynamic amplifiers; using switched capacitors as resistors in differential amplifiers H03F3/45 takes precedence

Abstract

A switched operation amplifier including a biased circuit, an amplifier circuit, and a buffer circuit is provided. The biased circuit is to provide a first, a second, and a third biased signals by means of an input signal and a reference current source. The amplifier circuit is driven by the biased signals through current mirrors, a sample-and-hold switch, a complementary sample-and-hold switch and a differential pair. The buffer circuit includes a capacitor and two transistors in series. An output signal is generated from a node in between the two transistors, and fed back to a negative terminal of the differential pair of the amplifier circuit. The amplifier circuit charges the capacitor and controls one of the transistors of the buffer circuit until the voltages of a positive and the negative terminal of the differential pair are equal. By means of the operation of the switched op amplifier, the output voltage can be kept being stable.

Claims

1. A switched operation amplifier comprising:

a biased circuit, providing a first, a second, and a third biased signal;

a amplifier circuit, having a first transistor, a second differential pair, a third, a fourth, a fifth current mirror, a sample-and-hold switch, and a complementary sample-and-hold switch, wherein said first transistor is controlled by said first biased signal so as to provide two reference currents for said third, and fourth current mirror, which are, respectively, connected with two transistors of said second differential pair, further, a mirror current of said third current mirror being controlled by said third biased signal to determine whether said third mirror current of said third current mirror is fed into a reference terminal of said fifth current mirror or not, and still a mirror current terminal of said fourth current mirror being connected with both of said sample-and-hold switch and said complementary sample-and-hold switch so as to provide a current path either though said sample-and-hold switch to a mirror terminal of said fifth current mirror, or said complementary sample-and-hold switch to ground depending on sampling mode or holding mode being selected, still two gates of said two transistors of said second differential pair served, respectively, as a positive and a negative terminal; and

a buffer circuit having a capacitor, a second and a third transistor wherein said capacitor connected between ground and a node connected both of said sample-and-hold switch and a gate of said second transistor, and still a source terminal of said second transistor connected with a drain terminal of said third transistor, furthermore, said source terminal of said second transistor is served as a signal output terminal and fed back to said negative terminal and said third transistor is controlled by said second biased signal.

2. The switched operation amplifier according to claim 1, wherein said biased circuit comprises a first current mirror, a biased signal generator, a low output impedance buffer, said first current mirror generated said second biased signal according to a reference current, and further said biased signal generator connected with a mirror terminal of said first current mirror to generate said first biased signal, and still said low output impedance buffer connected with said first current mirror to generate said third biased signal according to a biased input signal.

3. The switched operation amplifier according to claim 2, wherein said low output impedance buffer comprises a fourth transistor, a first differential pair, a second current mirror, wherein said fourth transistor is controlled by said second biased signal.

4. The switched operation amplifier according to claim 2, wherein said biased input signal is generated by a voltage division circuit consisting of resistors.

5. The switched operation amplifier according to claim 2, wherein said biased generator is a transistor having a gate and drain thereof connected together.

6. The switched operation amplifier according to claim 1, wherein said sample-and-hold switch is composed of a fifth transistor in series connected with a sixth transistor and both of them are controlled by said third biased signal while switching to sampling mode.

7. The switched operation amplifier according to claim 1, wherein said complementary sample-and-hold switch is a transistor having a source terminal connected with said fourth current mirror and is controlled by said third biased signal while switching to holding mode.

8. A method of operating a sample-and-hold circuit, for a switched operation amplifier, said switched operation amplifier comprising a biased circuit for generating a third biased signal, a amplifier circuit and a buffer circuit, said amplifier circuit having a second differential pair, a fourth, a fifth current mirror, a sample-and-hold switch, and a complementary sample-and-hold switch, and said buffer circuit having a capacitor, said method comprising the steps of:

charging said capacitor through said fourth current mirror and said fifth current mirror by turning on said sample-and-hold switch to do signal sampling, said capacitor providing a rising voltage to a negative terminal of said second differential pair until said negative terminal has the same voltage as an input voltage received by a positive terminal of said second differential pair; and

discharging said capacitor by turning off said sample-and-hold switch to do signal holding, while said complementary sample-and-hold switch is turned on to provide a current path for said fourth current mirror.

9. The method of operating a sample-and-hold circuit according to claim 8, wherein said sample-and-hold switch and said complementary sample-and-hold switch are controlled by said third biased signal, and one is activated while the other one is turned off according to signal holding or sampling.

10. The method of operating a sample-and-hold circuit according to claim 8, wherein said biased circuit comprises only one current source to generate biased signals for said amplifier circuit and said buffer circuit.

11. The method of operating a sample-and-hold circuit according to claim 8, wherein said current path provided by said complementary sample-and-hold switch is conducted to ground.