Device for amplitude adjustment and rectification made with MOS technology
First Claim
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1. A full-wave rectifier circuit which performs full-wave rectification on an input signal of an input terminal so as to produce a full-wave rectified signal, said full-wave rectifier circuit, comprising:
- an inversion amplifier;
an amplifier; and
an output circuit which produces the full-wave rectified signal in response to an output signal of the inversion amplifier and an output signal of the amplifier, so as to output the full-wave rectified signal to an output terminal as an output signal,wherein the inversion amplifier includes;
a first constant current source,a first field-effect transistor of a p-channel, which has a first source, a first gate, and a first drain,a second field-effect transistor of a p-channel, which has a second source, a second gate, and a second drain,a third field-effect transistor, of an n-channel, which has a third source, a third gate, and a third drain,a fourth field-effect transistor of an n-channel, which has a fourth source, a fourth gate, and a fourth drain,wherein the first source is connected to the second source and a first terminal of the first constant current source,the first gate is connected to the input terminal via a first resistor and is connected to the output terminal via a second resistor,the first drain is connected to the third gate, the third drain, and the fourth gate,the second gate is supplied with a reference voltage,the second drain is connected to the fourth drain,the third source and the fourth source are grounded, anda second terminal of the first constant current source is connected to a power source,wherein the amplifier includes;
a second constant current source,a fifth field-effect transistor of a p-channel, which has a fifth source, a fifth gate, and a fifth drain,a sixth field-effect transistor of a p-channel, which has a sixth source, a sixth gate, and a sixth drain,a seventh field-effect transistor of an n-channel, which has a seventh source, a seventh gate, and a seventh drain,an eighth field-effect transistor of an n-channel, which has an eighth source, an eighth gate, and an eighth drain,wherein the fifth source is connected to the sixth source and a first terminal of the second constant current source,the fifth gate is connected to the input terminal,the fifth drain is connected to the seventh drain,the sixth gate is connected to the output terminal,the sixth drain is connected to the seventh gate, the eighth gate, and the eighth drain,the seventh source is and the eighth source are grounded, anda second terminal of the second constant source is connected to the power source, wherein the output circuit includes;
a third constant current source,a ninth field-effect transistor of an n-channel, which has a ninth source, a ninth gate, and a ninth drain,a tenth field-effect transistor of an n-channel, which has a tenth source, a tenth gate, and a tenth drain, andwherein the ninth drain is connected to the tenth drain, a first terminal of the third constant source, and the output terminal,the ninth gate is connected to the fourth drain and the second drain,the ninth source and the tenth source are grounded,the tenth gate is connected to the fifth drain and the seventh drain, anda second terminal of the third constant current source is connected to the power source,wherein the output signal of the output terminal is subjected to negative feedback to the first gate and the sixth gate, andwherein the input signal of the input terminal is supplied to the fifth gate and is supplied to the first fate via the first resistor, so that a first gate voltage is supplied to the ninth gate while a second gate voltage whose phase is inverse to a phase of the first gate voltage is supplied to the tenth gate, whereby a current corresponding to one of the first gate voltage and the second gate voltage is forced to selectively flow through one of the ninth field-effect transistor and the tenth field-effect transistor, so that the full-wave rectified signal whose level is lower than a level of the reference voltage is produced and is output to the output terminal as the output signal.
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Abstract
An amplitude adjustment device such as an amplitude compression device and amplitude expansion device is basically configured by a PWM modulator, a demodulator and an amplitude detector. Herein, the PWM modulator effects pulse-width modulation on an input signal to produce a pulse-width modulated signal, which is demodulated by the demodulator to produce an output signal. In addition, the amplitude detector detects an amplitude of a demodulated signal or an amplitude of the input signal to produce a control signal. A modulation factor of the pulse-width modulation is adjusted based on the control signal. In the case of the amplitude compression device, an input/output gain is changed inversely proportional to the amplitude of the input signal or amplitude of the output signal. Thus, it is possible to compress a dynamic range with respect to input/output characteristics. A full-wave rectifier, applicable to the amplitude adjustment device, is mainly configured by an inversion amplifier, an amplifier and an output section. Herein, the inversion amplifier amplifies an input signal with a gain of “−1”, while the amplifier amplifies it with a gain of “1”. Outputs of the amplifiers differ from each other in phases by 180°. The output section produces a full-wave rectified signal based on the outputs of the amplifiers. Incidentally, all of the amplifiers and output section are configured using field-effect transistors without using diodes being externally connected. Hence, it is possible to manufacture the full-wave rectifier in a form of an IC in accordance with the MOS process with ease.
15 Citations
3 Claims
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1. A full-wave rectifier circuit which performs full-wave rectification on an input signal of an input terminal so as to produce a full-wave rectified signal, said full-wave rectifier circuit, comprising:
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an inversion amplifier; an amplifier; and an output circuit which produces the full-wave rectified signal in response to an output signal of the inversion amplifier and an output signal of the amplifier, so as to output the full-wave rectified signal to an output terminal as an output signal, wherein the inversion amplifier includes; a first constant current source, a first field-effect transistor of a p-channel, which has a first source, a first gate, and a first drain, a second field-effect transistor of a p-channel, which has a second source, a second gate, and a second drain, a third field-effect transistor, of an n-channel, which has a third source, a third gate, and a third drain, a fourth field-effect transistor of an n-channel, which has a fourth source, a fourth gate, and a fourth drain, wherein the first source is connected to the second source and a first terminal of the first constant current source, the first gate is connected to the input terminal via a first resistor and is connected to the output terminal via a second resistor, the first drain is connected to the third gate, the third drain, and the fourth gate, the second gate is supplied with a reference voltage, the second drain is connected to the fourth drain, the third source and the fourth source are grounded, and a second terminal of the first constant current source is connected to a power source, wherein the amplifier includes; a second constant current source, a fifth field-effect transistor of a p-channel, which has a fifth source, a fifth gate, and a fifth drain, a sixth field-effect transistor of a p-channel, which has a sixth source, a sixth gate, and a sixth drain, a seventh field-effect transistor of an n-channel, which has a seventh source, a seventh gate, and a seventh drain, an eighth field-effect transistor of an n-channel, which has an eighth source, an eighth gate, and an eighth drain, wherein the fifth source is connected to the sixth source and a first terminal of the second constant current source, the fifth gate is connected to the input terminal, the fifth drain is connected to the seventh drain, the sixth gate is connected to the output terminal, the sixth drain is connected to the seventh gate, the eighth gate, and the eighth drain, the seventh source is and the eighth source are grounded, and a second terminal of the second constant source is connected to the power source, wherein the output circuit includes; a third constant current source, a ninth field-effect transistor of an n-channel, which has a ninth source, a ninth gate, and a ninth drain, a tenth field-effect transistor of an n-channel, which has a tenth source, a tenth gate, and a tenth drain, and wherein the ninth drain is connected to the tenth drain, a first terminal of the third constant source, and the output terminal, the ninth gate is connected to the fourth drain and the second drain, the ninth source and the tenth source are grounded, the tenth gate is connected to the fifth drain and the seventh drain, and a second terminal of the third constant current source is connected to the power source, wherein the output signal of the output terminal is subjected to negative feedback to the first gate and the sixth gate, and wherein the input signal of the input terminal is supplied to the fifth gate and is supplied to the first fate via the first resistor, so that a first gate voltage is supplied to the ninth gate while a second gate voltage whose phase is inverse to a phase of the first gate voltage is supplied to the tenth gate, whereby a current corresponding to one of the first gate voltage and the second gate voltage is forced to selectively flow through one of the ninth field-effect transistor and the tenth field-effect transistor, so that the full-wave rectified signal whose level is lower than a level of the reference voltage is produced and is output to the output terminal as the output signal.
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2. A full-wave rectifier circuit according to claim 1, wherein the first resistor and the second resistor have a same resistance.
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3. A full-wave rectifier circuit which performs full-wave rectification on an input signal of an input terminal so as to produce a full-wave rectified signal, said full-wave rectifier circuit, comprising:
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an inversion amplifier; an amplifier; and an output circuit which produces the full-wave rectified signal in response to an output signal of the inversion amplifier and an output signal of the amplifier, so as to output the full-wave rectified signal to an output signal as an output signal, wherein the inversion amplifier includes; a first constant current source, a first field-effect transistor of a p-channel, which has a first source, a first gate, and a first drain, a second field-effect transistor of a p-channel, which has a second source, a second gate, and a second drain, a third field-effect transistor of an n-channel, which has a third source, a third gate, and a third drain, a fourth field-effect transistor of an n-channel, which has a fourth source, a fourth gate, and a fourth drain, wherein the first source is connected to the second source and a power source, the first fate is connected to the second gate, the first drain, and the third drain, the second drain is connected to the fourth drain, the third gate is connected to the input terminal via a first resistor and is connected to the output terminal via a second resistor, the third source is connected to the fourth source and a first terminal of the first constant current source, the fourth gate is supplied with a reference voltage, and a second terminal of the first constant current source is grounded, wherein the amplifier includes; a second constant current source, the fifth field-effect transistor of a p-channel, which has a fifth source, a fifth gate, and a fifth drain, a sixth field-effect transistor of a p-channel, which has a sixth source, a sixth gate, and a sixth drain, a seventh field-effect transistor of an n-channel, which has a seventh source, a seventh gate, and a seventh drain, an eighth field-effect transistor of an n-channel, which has an eighth source, an eighth gate, and an eighth drain, wherein the fifth source is connected to the sixth source, and the power source, the fifth gate is connected to the sixth gate, the sixth drain, and the eighth drain, the fifth drain is connected to the seventh drain, the seventh gate is connected to the input terminal, the seventh source is connected to the first terminal of the second constant current source and the eighth source, the eighth gate is connected to the output terminal, and a second terminal of the second constant current source is grounded, wherein the output circuit includes; a third constant current source, a ninth field-effect transistor of a p-channel, which has a ninth source, a ninth gate, and a ninth drain, a tenth field-effect transistor of a p-channel, which has a tenth source, a tenth gate, and a tenth drain, wherein the ninth gate is connected to the second drain and the fourth drain, the ninth source and the tenth source are connected to the power source, the ninth-drain is connected to the tenth drain, a first terminal of the third constant current source, and the output terminal, the tenth gate is connected to the fifth drain and the seventh drain, and a second terminal of the third constant current source is grounded, wherein the output signal of the output terminal is subjected to negative feedback to the third gate and the eighth gate, wherein the input signal of the input terminal is supplied to the seventh gate and is supplied to the third gate via the first resistor, so that a first gate voltage is supplied to the ninth gate while a second gate voltage whose phase is inverse to a phase of the first gate voltage is supplied to the tenth gate, whereby a current corresponding to one of the first gate voltage and the second gate voltage is forced to selectively flow through one of the ninth field-effect transistor and the tenth field-effect transistor, so that the full-wave rectified signal whose level is higher than a level of the reference voltage is produced and is output to the output terminal as the output signal.
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Specification
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Current AssigneeYamaha Corporation
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Original AssigneeYamaha Corporation
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InventorsMaejima, Toshio
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Primary Examiner(s)Vu; Bao Q.
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Application NumberUS11/027,983Publication NumberTime in Patent Office854 DaysField of Search330/253, 330/257, 330/135, 330/277US Class Current330/10CPC Class CodesH03G 3/3026 the gain being discontinuou...H03K 7/08 Duration or width modulatio...
