Liquid crystal display device

• US 7,215,310 B2
• Filed: 03/14/2002
• Issued: 05/08/2007
• Est. Priority Date: 03/20/2001
• Status: Expired due to Term

• Current Assignee: LG Display Co., Ltd.
• Original Assignee: LG Philips LCD Company Limited (LG Display Co., Ltd.)
• Inventors: Kwon, Keuk Sang, Song, Hong Sung
• Primary Examiner(s): Eisen; Alexander
• Application Number:
  US10/096,911
• Publication Number:
  US 20020163488A1
• Time in Patent Office: 1,881 Days
• Field of Search: 345 87-104, 345/204, 345211-213, 345/205
• US Class Current: 345/94
• CPC Class Codes: G09G 2300/0876 Supplementary capacities in pixels having special driving circuits and electrodes instead of being connected to common electrode or ground; Use of additional capacitively coupled compensation electrodes
• CPC Class Codes: G09G 2320/0247 Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
• CPC Class Codes: G09G 3/3614 Control of polarity reversal in general
• CPC Class Codes: G09G 3/3648 using an active matrix G09G3/367 - G09G3/3696 take precedence
• CPC Class Codes: G09G 3/3659 the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes

Abstract

A liquid crystal display device includes a plurality of data lines on a liquid crystal display panel, a plurality of gate lines on the liquid crystal display panel orthogonal to the plurality of data lines, a plurality of thin film transistors on the liquid crystal display panel, each arranged at intersections between the data lines and the gate lines, a plurality of pixels, each arranged at the intersections between the data lines and the gate lines, a gate driver for applying a scanning pulse to the gate lines, a data driver for applying data to the data lines, a timing controller for applying a timing signal to the gate driver and the data driver, a host controller for applying the data to the data driver and applying a horizontal synchronizing signal having a first frequency and a vertical synchronizing signal having a second frequency less than 60 Hz to the timing controller to control the data driver and the timing controller, a plurality of auxiliary lines, each provided on the liquid crystal display panel for applying a first voltage, and a plurality of storage capacitors, each connected to a corresponding one of the auxiliary lines to charge a second voltage from the auxiliary line in a scanning interval of a pre-stage scanning line.

Claims

1. A liquid crystal display device, comprising:

a plurality of data lines on a liquid crystal display panel;

a plurality of gate lines on the liquid crystal display panel orthogonal to the plurality of data lines;

a plurality of thin film transistors on the liquid crystal display panel, each arranged at intersections between the data lines and the gate lines;

a plurality of pixels, each pixel arranged at the intersections between the data lines and the gate lines;

a gate driver for applying a scanning pulse to the gate lines, wherein each gate line corresponds to one row of pixels;

a data driver for applying data to the data lines;

a timing controller for applying a timing signal to the gate driver and the data driver;

a host controller for applying the data to the data driver and applying a horizontal synchronizing signal having a first frequency and a vertical synchronizing signal having a second frequency less than 60 Hz to the timing controller to control the data driver and the timing controller;

a plurality of auxiliary lines connected to a common voltage source, each auxiliary line provided on the liquid crystal display panel for applying a first voltage; and

a plurality of storage capacitors, each connected to a corresponding one of the auxiliary lines to charge a second voltage from the data line in a scanning interval of a scanning line.

2. The device according to claim 1, wherein the storage capacitor of one pixel is commonly connected to the storage capacitor of a horizontally adjacent pixel.

3. The device according to claim 1, wherein the second frequency of the vertical synchronizing signal is about 30 Hz.

4. The device according to claim 1, wherein the host controller includes:

a data controller for applying the data to the data driver;

a vertical synchronizing signal oscillator for generating the vertical synchronizing signal; and

a horizontal synchronizing signal oscillator for generating the horizontal synchronizing signal.

5. The device according to claim 1, wherein the liquid crystal display device is driven by a 1-dot inversion system.

6. The device according to claim 1, wherein the liquid crystal display device is driven by a 2-dot inversion system.

7. A method for driving a liquid crystal display device that includes a plurality of data lines on a liquid crystal display panel, a plurality of gate lines on the liquid crystal display panel orthogonal to the plurality of data lines, a plurality of thin film transistors on the liquid crystal display panel, each arranged at intersections between the data lines and the gate lines, and a plurality of pixels, each pixel arranged at the intersections between the data lines and the gate lines, the method comprising:

applying a scanning pulse to the gate lines using a gate driver, wherein each gate line corresponds to one row of pixels;

applying data to the data lines using a data driver;

applying a timing signal to the gate driver and the data driver using a timing controller;

applying the data to the data driver and applying a horizontal synchronizing signal having a first frequency and a vertical synchronizing signal having a second frequency less than 60 Hz to the timing controller to control the data driver and the timing controller using a host controller;

applying a first voltage to a plurality of auxiliary lines from a common voltage source connected thereto, each auxiliary line provided on the liquid crystal display panel; and

charging a plurality of storage capacitors, each connected to a corresponding one of the auxiliary lines, with a second voltage from the data line during a scanning interval of a scanning line.

8. The method according to claim 7, wherein the storage capacitor of one pixel is commonly connected to the storage capacitor of a horizontally adjacent pixel.

9. The method according to claim 7, wherein the second frequency of the vertical synchronizing signal is about 30 Hz.

10. The method according to claim 7, wherein the host controller includes:

a data controller for applying the data to the data driver;

a vertical synchronizing signal oscillator for generating the vertical synchronizing signal; and

a horizontal synchronizing signal oscillator for generating the horizontal synchronizing signal.

11. The method according to claim 7, further including driving the liquid crystal display device by a 1-dot inversion system.

12. The method according to claim 7, further including driving the liquid crystal display device by a 2-dot inversion system.

13. The method according to claim 12, wherein a polarity of the data applied to the data driver is inverted at every two horizontal synchronous intervals.

14. The method according to claim 13, wherein the two horizontal synchronous intervals correspond to two gate line intervals.

15. The method according to claim 12, wherein a polarity of the data applied to the data driver is inverted every frame.

16. A liquid crystal display device, comprising:

a liquid crystal display panel;

a plurality of gate lines on the liquid crystal display panel;

a plurality of data lines on the liquid crystal display panel orthogonal to the plurality of gate lines;

a plurality of auxiliary lines on the liquid crystal display panel connected to a common voltage source for applying a first voltage;

a plurality of thin film transistors, each at intersections between the gate lines and data lines;

a plurality of liquid crystal cells, each connected to one of the thin film transistors, wherein the thin film transistors corresponding to one row of the liquid crystal cells are commonly connected to one gate line;

a host controller for applying a horizontal synchronizing signal having a first frequency and a vertical synchronizing signal having a second frequency of about 30 Hz; and

a plurality of storage capacitors, each corresponding to one of the liquid crystal cells, wherein the storage capacitors of laterally adjacent liquid crystal cells are electrically interconnected via at least one of the auxiliary lines and are charged with a second voltage from a corresponding one of the data lines during application of a gate signal to the gate line.

17. The device according to claim 16, wherein a first electrode of each liquid crystal cell is commonly connected to a first electrode of each storage capacitor and a drain electrode of each thin film transistor.

18. The device according to claim 17, wherein a second electrode of each liquid crystal cell is electrically connected to a common voltage terminal.

19. A liquid crystal display device, comprising:

a liquid crystal display panel;

a plurality of thin film transistors on the liquid crystal display panel;

a plurality of pixels, each corresponding to the thin film transistors, wherein each of the thin film transistors in one row of pixels are commonly connected to one scanning line;

a plurality of auxiliary lines connected to a common voltage source, each auxiliary line provided on the liquid crystal display panel for applying a first voltage;

a host controller for applying a horizontal synchronizing signal having a first frequency and a vertical synchronizing signal having a second frequency of about 30 Hz; and

a plurality of storage capacitors, each connected to a corresponding one of the auxiliary lines to charge a second voltage from a data line in a scanning interval of the scanning line.

20. The device according to claim 19, wherein the storage capacitor of one pixel is commonly connected to the storage capacitor of a horizontally adjacent pixel.