Multi-layered memory cell structure

• US 7,215,563 B2
• Filed: 02/25/2005
• Issued: 05/08/2007
• Est. Priority Date: 04/02/2004
• Status: Expired due to Fees

• Current Assignee: Duncan G. Elliott, Tyler L. Brandon
• Original Assignee: Duncan G. Elliott, Tyler L. Brandon
• Inventors: Elliott, Duncan G., Brandon, Tyler L.
• Primary Examiner(s): Yoha; Connie C.
• Application Number:
  US10/906,594
• Publication Number:
  US 20050226068A1
• Time in Patent Office: 802 Days
• Field of Search: 365/94, 365/103, 365/104, 365/63
• US Class Current: 365/94
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 17/12 using field-effect devices
• CPC Class Codes: G11C 17/123 comprising cells having several storage transistors connected in series
• CPC Class Codes: H10B 20/00 Read-only memory [ROM] devices
• CPC Class Codes: H10B 20/363 Gate conductor programmed

Abstract

A high-density memory device and design method that utilizes some or all of the existing stacked process conductor layers provided by a manufacturing process to enhance the number of available bitlines and/or wordlines within the memory device. The memory device includes a plurality of memory cells arranged in columns and rows, a plurality of wordlines, a plurality of bitlines, at least one via-stack, wherein said existing stacked process conductor layers are used to implement at least one additional wordline or bitline. The via-stacks consist of a plurality of vias, are located close to a memory cell, and adapted to electrically connect the memory cell to multiple bitlines or multiple wordlines or both0. This design method increases the number of possible connections to or from each individual memory cell. When this design method is combined with varied configurations of basic underlying ROM cell types, even further increased cell density can be achieved.

Claims

1. A multi-layered memory device for storing data and subsequently reading out the stored data, said memory device utilizing a plurality of existing stacked process conductor layers, said memory device comprising:

(a) plurality of memory cells arranged in columns and rows, each memory cell including at least one transistor, each transistor being adapted to store information;

(b) plurality of wordlines corresponding to the plurality of rows, each wordline being used in common in each row of said memory cells, at least one of said wordlines being connected to a corresponding memory cell in the column of memory cells;

(c) plurality of bitlines, said bitlines arranged substantially orthogonal to said wordlines, at least one of said bitlines being used in common for data read-out along a column of memory cells;

(d) at least one via-stack, said via-stack comprising a plurality of vias positioned to connect adjacent conduction layers, said via-stack being arranged in close proximity to at least one memory cell, said via-stack being adapted to electrically connect at least one transistor within at least one memory cell to at least one of the existing stacked process conductor layers;

wherein said existing stacked process conductor layers are used to implement within the multi-layered memory device, at least one of an additional wordline as defined in (b) and an additional bitline as defined in (c).

2. The memory device of claim 1, wherein said existing stacked process conductor layers are used to implement a plurality of additional bitlines within the device.

3. The memory device of claim 1, wherein said existing stacked process conductor layers are used to implement a plurality of additional wordlines within the device.

4. The memory device of claim 1, wherein at least one of said via-stacks has a height less than the height of the existing stacked process conductor layers in order to allow for at least one conductor layer within said existing stacked process conductor layers to run over top of said via-stack.

5. The memory device of claim 1, wherein said existing stacked process conductor layers includes at least one crossover conductor layer for electrically connecting to the transistor of a first memory cell through a first via-stack and to the transistor of a second memory cell through a second via-stack.

6. The memory device of claim 1, wherein said memory device includes a series of adjacent memory cells, each adjacent memory cell having a different value.

7. The memory device of claim 1, wherein each memory cell is associated with at least two bitlines.

8. The memory device of claim 1, wherein each memory cell is associated with at least two wordlines.

9. The memory device of claim 1, wherein said memory device is a ROM device and wherein each memory cell contains one transistor and is associated with at least four bitlines.

10. The memory device of claim 1, wherein said memory device is a ROM device and wherein each memory cell contains two transistors and is associated with at least five bitlines.

11. The memory device of claim 1, wherein said memory device is a ROM device and wherein each memory cell contains four transistors and is associated with at least ten bitlines.

12. The memory device of claim 1, wherein said information stored by each said memory cell is non-integer number of bits.

13. The memory device of claim 1, wherein said memory device is a hybrid multi-valued ROM device utilizing at least one multi-valued transistor to provide multiple drives, and wherein said at least one multi-valued transistor are selectively associated with two or more bitlines.

14. The memory device of claim 1, wherein said memory device is a hybrid multi-valued ROM device utilizing a set of multi-valued transistors to provide multiple drives, and wherein each said memory cell contains two transistors selected from said set of multi-valued transistors and is associated with two wordlines and one via-stack.

15. The memory device of claim 1, wherein said memory device is a hybrid multi-valued ROM device utilizing a set of multi-valued transistors to provide multiple drives, and wherein each said memory cell contains one transistors selected from said set of multi-valued transistors and is associated with one wordline and one via-stack.

16. The memory device of claim 1, wherein said memory device is a combination ROM-RAM memory device comprising a ROM memory structure implemented over a RAM memory structure, wherein a plurality of bitlines are selectively connected to said RAM memory structure at the time of manufacture.

17. The memory device of claim 1, wherein each memory cell contains at least two transistors, and wherein each transistor within each memory cell is selectively associated or unassociated with a bitline.

18. The memory device of claim 1, wherein each memory cell is one of a plurality of cell types to allow for a diversity of information storage capacity amongst memory cells, wherein each cell type is configured at the time of manufacture to allow for a maximum amount of bitline selection selected from the group consisting of none, one, and greater than one.

20. The method of claim 18, further comprising the step of using the existing stacked process conductor layers to implement a plurality of additional bitlines within the device.

21. The method of claim 18 further comprising the step of using the existing stacked process conductor layers to implement a plurality of additional wordlines within the device.

22. The method of claim 18, further comprising the step of forming at least one via-stack having a height less than the height of the existing stacked process conductor layers and forming at least one conductor layer within said existing stacked process conductor layers such that said conductor layer runs over top of said via-stack.

23. The method of claim 18, further comprising the step of forming at least one crossover conductor layer for electrically connecting to the transistor of a first memory cell through a first via-stack and to the transistor of a second memory cell through a second via-stack.

24. The method of claim 18, further comprising the step of forming said memory device such that it includes a series of adjacent memory cells, each adjacent memory cell having a different value.

25. The method of claim 18, wherein each memory cell contains at least two bitlines.

26. The method of claim 18, wherein each memory cell contains at least two wordlines.

27. The method of claim 18, wherein said memory device is a ROM device and wherein each memory cell is manufactured to contain one transistor and to be associated with at least four bitlines.

28. The method of claim 18, wherein said memory device is a ROM device and wherein each memory cell is manufactured to contain two transistors and to be associated with at least five bitlines.

29. The method of claim 18, wherein said memory device is a ROM device and wherein each memory cell is manufactured to contain four transistors and to be associated with at least ten bitlines.

30. The method of claim 18, wherein said information stored by each said memory cell is non-integer number of bits.

31. The method of claim 18, wherein said memory device is a hybrid multi-valued ROM device utilizing at least one multi-valued transistor to provide multiple drives, and wherein said at least one multi-valued transistor are selectively associated with two or more bitlines.

32. The method of claim 18, wherein said memory device is a hybrid multi-valued ROM device utilizing a set of multi-valued transistors to provide multiple drives, and wherein each said memory cell is manufactured to contain two transistors selected from said set of multi-valued transistors and to be associated with two wordlines and one via-stack.

33. The method of claim 18, wherein said memory device is a hybrid multi-valued ROM device utilizing a set of multi-valued transistors to provide multiple drives, and wherein each said memory cell is manufactured to contain one transistor selected from said set of multi-valued transistors and to be associated with one wordline and one via-stack.

34. The method of claim 18, wherein said memory device is manufactured to be a combination ROM-RAM memory device comprising a ROM memory structure implemented over a RAM memory structure, wherein a plurality of bitlines are selectively connected to said RAM memory structure at the time of manufacture.

35. The method of claim 18, wherein each memory cell contains at least two transistors, and wherein each transistor within each memory cell is selectively associated or unassociated with a bitline.

36. The method of claim 18, wherein each memory cell is one of a plurality of cell types to allow for a diversity of information storage capacity amongst memory cells, wherein each cell type is configured at the time of manufacture to allow for a maximum amount of bitline selection selected from the group consisting of none, one, and greater than one.

19. A method of manufacturing a multi-layered memory device for storing data and subsequently reading out the stored data, said method utilizing existing stacked process conductor layers, said method comprising:

(a) providing and arranging a plurality of memory cells in columns and rows, each memory cell including at least one transistor, each transistor being adapted to store information;

(b) providing a plurality of wordlines corresponding to the plurality of rows, each wordline being used in common in each row of said memory cells, at least one of said wordlines being connected to a corresponding memory cell in the column of memory cells;

(c) providing and arranging a plurality of bitlines substantially orthogonal to said wordlines, at least one of said bitlines being used in common for data read-out along a column of memory cells;

(d) providing a via-stack by positioning a plurality of vias coupling conductive layers, and arranging said via-stack in close proximity to at least one memory cell, said via-stack being adapted to electrically connect at least one transistor within the at least one memory cell to at least one of the existing stacked process conductor layers;

wherein the existing stacked process conductor layers are used to implement within the memory device at least of an additional wordline as defined in (b) and a bitline as defined in (c).