Non-volatile memory control

• US 7,215,580 B2
• Filed: 06/14/2004
• Issued: 05/08/2007
• Est. Priority Date: 09/28/2001
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Lexar Media Incorporated (Micron Technology, Inc.)
• Inventors: Gorobets, Sergey Anatolievich
• Primary Examiner(s): Nguyen; Viet Q.
• Application Number:
  US10/867,800
• Publication Number:
  US 20050018527A1
• Time in Patent Office: 1,058 Days
• Field of Search: 365/189.02, 365/189.04, 365/239, 710/61, 711/167, 711/168, 711/169
• US Class Current: 365/189.02
• CPC Class Codes: G06F 13/1615 using a concurrent pipeline structrure
• CPC Class Codes: G06F 13/4239 with asynchronous protocol
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

According to an embodiment of the present invention, there is provided a method and apparatus for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays from a plurality of available arrays accessed at one time, wherein the method comprises implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays and limiting the number of active arrays operating at one time, the arrangement being such that the controller waits for the at least one of the arrays to complete before initiating the transfer to and from a further array.

Claims

1. A method for use in a memory system having a non-volatile memory and a controller for limiting the number of non-volatile memory arrays, within the non-volatile memory, from a plurality of available arrays accessed at one time, the method comprising:

implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays;

before accessing any array, checking the number of currently active arrays against an allowed limit; and

waiting for the at least one of the arrays to complete before initiating the transfer to and from a further array,

thereby controlling flash memory accesses in a memory system configured to use concurrent operation in different flash memory arrays and allowing performance to be changed easily in systems supporting concurrent flash operations in different Flash arrays.

2. A non-volatile memory system which presents the logical characteristics of a disk storage device to a host system comprising:

a non-volatile memory incorporating a plurality of memory arrays; and

a controller including,

means for implementing a pipelining sequence for transferring data to and from the non-volatile memory arrays; and

means for limiting the number of active arrays operating at one time, before accessing any array, checking the number of currently active arrays against an allowed limit, thereby controlling flash memory accesses in a memory system configured to use concurrent operation in different flash memory arrays and allowing performance to be changed easily in systems supporting concurrent flash operations in different Flash arrays.