Tracking circuit for a memory device

• US 7,215,587 B2
• Filed: 07/05/2005
• Issued: 05/08/2007
• Est. Priority Date: 07/05/2005
• Status: Expired due to Fees

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lee, Cheng Hung, Liao, Hung-Jen, Wang, Simon
• Primary Examiner(s): Dinh; Son
• Assistant Examiner(s): Nguyen; Hien N
• Application Number:
  US11/172,873
• Publication Number:
  US 20070008771A1
• Time in Patent Office: 672 Days
• Field of Search: 365/203, 365/200, 365190-193, 365194-195, 365/154, 365/49
• US Class Current: 365/200
• CPC Class Codes: G11C 11/419 Read-write [R-W] circuits
• CPC Class Codes: G11C 7/14 Dummy cell management; Sense reference voltage generators
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 7/227 Timing of memory operations based on dummy memory elements or replica circuits

Abstract

A memory device includes a memory array, an I/O circuit for accessing the memory array, and a tracking circuit. The tracking circuit includes a dummy bit line, a first tracking cell including a first NMOS transistor, the first tracking cell being coupled to receive a control signal and also coupled to the dummy bit line through the first NMOS transistor, and a second tracking cell including a second NMOS transistor, the second tracking cell being coupled to receive the control signal and also coupled to the dummy bit line through the second NMOS transistor, a gate of the second NMOS transistor being coupled to the dummy bit line. The memory device also includes a control circuit coupled to the dummy bit line for generating a clock signal for the I/O circuit.

Claims

1. A memory device, comprising:

a memory array;

an I/O circuit for accessing the memory array;

a tracking circuit including

a dummy bit line,

a first tracking cell including a first NMOS transistor, the first tracking cell being coupled to receive a control signal and also coupled to the dummy bit line through the first NMOS transistor, and

a second tracking cell including a second NMOS transistor, the second tracking cell being coupled to receive the control signal and also coupled to the dummy bit line through the second NMOS transistor, a gate of the second NMOS transistor being coupled to the dummy bit line; and

a control circuit coupled to the dummy bit line for generating a clock signal for the I/O circuit.

2. The memory device of claim 1, wherein the memory array includes a plurality of memory cells each having a 6-transistor structure.

3. The memory device of claim 1, wherein the I/O circuit includes one or more sense amplifiers.

4. The memory device of claim 1, further comprising a word line decoder coupled to receive the control signal as a clock signal for decoding word line address signals.

5. The memory device of claim 1, wherein the control circuit includes one or more inverters coupled between the dummy bit line and the I/O circuit.

6. The memory device of claim 1, wherein the memory array includes a plurality of memory cells arranged in a plurality of rows each corresponding to one of a plurality of word lines and a plurality of columns each corresponding to one of a plurality of pairs of bit lines, and wherein the I/O circuit and the tracking circuit are on opposite sides of the memory array along a direction of the bit lines.

7. The memory device of claim 1, wherein the first NMOS transistor has a gate coupled to receive the control signal and a drain coupled to the dummy bit line.

8. The memory device of claim 1, wherein the second NMOS transistor has a drain coupled to the dummy bit line.

9. The memory device of claim 1, wherein the first tracking cell includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, each of the first PMOS transistor, the second PMOS transistor, the first NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor having a gate, a source, a drain, and a substrate, wherein

the gate of the first PMOS transistor, the gate of the third NMOS transistor, the drain of the second PMOS transistor, the drain of the fourth NMOS transistor, and the drain of the fifth NMOS transistor are all coupled to one another and further coupled to a power supply voltage,

the gate of the second PMOS transistor, the gate of the fourth NMOS transistor, the drain of the first PMOS transistor, the drain of the third NMOS transistor, and the drain of the first NMOS transistor are all coupled to one another,

the substrates and sources of the first and second PMOS transistors are all coupled to the power supply voltage,

the substrates and the sources of the third and fourth NMOS transistors and the substrates of the first and fifth NMOS transistors are grounded,

the drain of the first NMOS transistor is coupled to the dummy bit line and the drain of the fifth NMOS transistor is coupled to another dummy bit line, and

the gate of the first NMOS transistor is coupled to receive the control signal and the gate of the fifth NMOS transistor is coupled to receive a word line signal.

10. The memory device of claim 1, wherein the second tracking cell further includes a first PMOS transistor, a second PMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor, each of the first PMOS transistor, the second PMOS transistor, the second NMOS transistor, the third NMOS transistor, the fourth NMOS transistor, and the fifth NMOS transistor having a gate, a source, a drain, and a substrate, wherein

the gate of the first PMOS transistor and the gate of the third NMOS transistor are both coupled to receive the control signal,

the gate of the second PMOS transistor, the gate of the fourth NMOS transistor, the drain of the first PMOS transistor, and the drain of the third NMOS transistor, and the source of the second NMOS transistor are all coupled to one another,

the substrates and sources of the first and second PMOS transistors are all coupled to a power supply voltage,

the substrates and sources of the third and fourth NMOS transistors and the substrates of the second and fifth NMOS transistors are all grounded,

the drain of the second NMOS transistor is coupled to the dummy bit line, and

the gate of the fifth NMOS transistor is coupled to receive a word line signal, the drain of the fifth NMOS transistor is coupled to another dummy bit line, and the source of the fifth NMOS transistor is floating.

11. The memory device of claim 1, the tracking circuit further comprising one or more third tracking cells each structured substantially the same as the first tracking cell.

12. The memory device of claim 1, the tracking circuit further comprising one or more third tracking cells each structured substantially the same as the second tracking cell.

13. A memory device, comprising:

a plurality of memory arrays;

a plurality of I/O circuits;

a plurality of control circuits; and

a plurality of tracking circuits each including

a dummy bit line,

a first tracking cell including a first NMOS transistor, the first tracking cell being coupled to receive a control signal and also coupled to the dummy bit line through the first NMOS transistor, and

a second tracking cell including a second NMOS transistor, the second tracking cell being coupled to receive the control signal and also coupled to the dummy bit line through the second NMOS transistor, a gate of the second NMOS transistor being coupled to the dummy bit line,

wherein each memory array corresponds to one of the plurality of I/O circuits, one of the plurality of tracking circuits, and one of the plurality of control circuits, and wherein, for each memory array, the corresponding control circuit is coupled to the dummy bit line of the corresponding tracking circuit for generating a clock signal for the corresponding I/O circuit.

14. The memory device of claim 13, wherein the memory arrays include a plurality of memory cells each having a 6-transistor structure.

15. The memory device of claim 13, wherein the I/O circuits include one or more sense amplifiers.

16. The memory device of claim 13, further comprising a plurality of word line decoders each operating on a clock signal for decoding word line address signals and a plurality of bit line decoders each operating on a clock signal for decoding bit line address signals, the clock signal for the word line decoders and the clock signal for the bit lien decoders being substantially synchronized to the control signal.

17. The memory device of claim 13, wherein the control circuits include one or more inverters coupled between the dummy bit line of the corresponding tracking circuit and the corresponding I/O circuit.

18. The memory device of claim 13, wherein at least one of the memory arrays includes a plurality of memory cells arranged in a plurality of rows each corresponding to one of a plurality of word lines and a plurality of columns each corresponding to one of a plurality of pairs of bit lines, and wherein the I/O circuit and the tracking circuit corresponding to the at least one of the memory arrays are on opposite sides of the at least one of the memory arrays along a direction of the bit lines.

19. The memory device of claim 13, wherein the first NMOS transistor has a gate coupled to receive the control signal and a drain coupled to the dummy bit line.

20. The memory device of claim 13, wherein the second NMOS transistor has a drain coupled to the dummy bit line.

21. The memory device of claim 13, each tracking circuit further comprising one or more third tracking cells each structured substantially the same as the first tracking cell.

22. The memory device of claim 13, each tracking circuit further comprising one or more third tracking cells each structured substantially the same as the second tracking cell.

23. A tracking circuit in a memory device, wherein the memory device includes a memory array, an I/O circuit for accessing the memory array, and a control circuit, wherein the tracking circuit is coupled to receive and delay a control signal for the control circuit to generate a clock signal for the I/O circuit, the tracking circuit comprising:

a dummy bit line;

one or more first tracking cells each including a first NMOS transistor, each of the first tracking cells being coupled to receive a control signal and also coupled to the dummy bit line through the first NMOS transistor; and

one or more second tracking cells each including a second NMOS transistor, each of the second tracking cells being coupled to receive the control signal and also coupled to the dummy bit line through the second NMOS transistor, a gate of the second NMOS transistor being coupled to the dummy bit line.

24. The tracking circuit of claim 23, wherein the memory array includes a plurality of memory cells arranged in a plurality of rows each corresponding to one of a plurality of word lines and a plurality of columns each corresponding to one of a plurality of pairs of bit lines, wherein the tracking circuit is on an opposite side of the memory array from the I/O circuit along a direction of the bit lines.