Logical separation and accessing of descriptor memories

• US 7,215,662 B1
• Filed: 03/22/2002
• Issued: 05/08/2007
• Est. Priority Date: 03/22/2002
• Status: Expired due to Fees

• Current Assignee: Juniper Networks Incorporated
• Original Assignee: Juniper Networks Incorporated
• Inventors: Lim, Raymond Marcelino Manese, Libby, Jeffrey G.
• Primary Examiner(s): Pham; Chi
• Assistant Examiner(s): JAIN, RAJ K
• Application Number:
  US10/102,933
• Time in Patent Office: 1,873 Days
• Field of Search: 370/392, 370/352, 370/353, 370/401, 370/389, 709/236, 709/230
• US Class Current: 370/352
• CPC Class Codes: H04L 2012/5665 Interaction of ATM with other protocols
• CPC Class Codes: H04L 45/00 Routing or path finding of packets in data switching networks routing or path finding in wireless networks H04W40/00
• CPC Class Codes: H04L 45/60 Router architectures
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3072 Packet splitting
• CPC Class Codes: H04L 49/602 Multilayer or multiprotocol switching, e.g. IP switching

Abstract

A packet header processing engine includes a memory having a number of distinct portions for respectively storing different types of descriptor information for a header of a packet. A packet header processing unit includes a number of pointers corresponding to the number of distinct memory portions. The packet header processing unit is configured to retrieve the different types of descriptor information from the number of distinct memory portions and to generate header information from the different types of descriptor information.

Claims

1. A packet header processing engine comprising:

a template memory configured to store template data;

a tag descriptor memory configured to store tag descriptor data;

a layer x (Lx) descriptor memory configured to store Lx descriptor data; and

an Lx header execution unit connected to the template memory, the tag descriptor memory, and the Lx descriptor memory and configured to construct an Lx header from at least one of the template data, the tag descriptor data, or the Lx descriptor data.

2. The packet header processing engine of claim 1, wherein the template memory, the tag descriptor memory, and the Lx descriptor memory are contiguous logical portions of a single descriptor memory.

3. The packet header processing engine of claim 2, wherein the Lx header execution unit is configured to store a template pointer, a tag pointer, and an Lx pointer that respectively point to the template memory, the tag descriptor memory, and the Lx descriptor memory portions of the single descriptor memory.

4. The packet header processing engine of claim 1, wherein the Lx header execution unit is configured to construct the Lx header from at least two of the template data, the tag descriptor data, or the Lx descriptor data.

5. A packet header processing engine comprising:

a memory configured to store at least one of template data, tag descriptor data, and layer x (Lx) descriptor data as continuous portions of the memory; and

a packet processing unit connected to the memory and configured to construct packet header information according to a packet header protocol from the at least one of the template data, the tag descriptor data, or the Lx descriptor data.

6. The packet header processing engine of claim 5, wherein the memory includes a template portion that stores the template data, and

wherein the packet processing unit includes a template pointer to the template data.

7. The packet header processing engine of claim 6, wherein the packet processing unit is configured to increment the template pointer when reading the template data from the template portion of the memory.

8. The packet header processing engine of claim 5, wherein the memory includes a tag descriptor portion that stores the tag descriptor data, and

wherein the packet processing unit includes a tag pointer to the tag descriptor data.

9. The packet header processing engine of claim 8, wherein the packet processing unit is configured to increment the tag pointer when reading the tag descriptor data from the tag descriptor portion of the memory.

10. The packet header processing engine of claim 5, wherein the memory includes an Lx descriptor portion that stores the Lx descriptor data, and

wherein the packet processing unit includes an Lx pointer to the Lx descriptor data.

11. The packet header processing engine of claim 10, wherein the packet processing unit is configured to increment the Lx pointer when reading the Lx descriptor data from the Lx descriptor portion of the memory.

12. The packet header processing engine of claim 10, wherein the packet processing unit is a layer 2 (L2) header execution unit, and the packet header protocol is an Lx header protocol.

13. A method comprising:

reading descriptor data from a memory;

incrementing at least one pointer to the descriptor data upon the reading; and

constructing packet header information from the descriptor data according to a packet header protocol.

14. The method of claim 13, wherein the reading includes:

reading descriptor data from at least one of multiple contiguous portions of the memory, and

wherein the incrementing includes;

incrementing at least one of multiple pointers corresponding to the portions of the memory read from.

15. The method of claim 14, wherein the reading further includes:

reading other descriptor data from another one of the multiple contiguous portions of the memory, and

wherein the incrementing further includes;

incrementing another one of the multiple pointers corresponding to the another one portion of the memory read from.

16. The method of claim 13, wherein the descriptor data includes at least one of template data, tag descriptor data, or layer 2 (L2) descriptor data.

17. The method of claim 14, wherein each of the multiple portions of the memory contain a different one of template data, tag descriptor data, or layer 2 (L2) descriptor data.

18. The method of claim 13, wherein the packet header protocol is a layer 2 (L2) protocol.

19. A network device for processing packets comprising:

a buffer configured to store the packets, including header data and payload data for the packets;

a descriptor reader component coupled to the buffer, the descriptor reader component configured to receive the header data for the packets stored in the buffer and configured to look up descriptor information relating to the received packet header data;

a memory coupled to the descriptor reader component, the memory including a plurality of distinct portions for receiving the descriptor information from the descriptor reader component; and

a packet header processing unit coupled to the descriptor reader component and including a plurality of pointers corresponding to the plurality of distinct memory portions, the packet header processing unit being configured to receive the packet header data from the descriptor reader component and the descriptor information from the plurality of distinct memory portions.

20. The network device of claim 19, wherein the packet header processing unit is further configured to generate packet header information from the packet header data and the descriptor information according to a packet header protocol.

21. The network device of claim 20, wherein the packet header protocol is a layer 2 (L2) protocol.

22. The network device of claim 19, wherein the plurality of distinct portions of the memory are three portions that respectively store template data, tag descriptor data, and layer 2 (L2) descriptor data.

23. A device comprising:

means for storing different types of packet header data;

means for successively reading the different types of packet header data from the means for storing using respective different pointers to the different types of packet header data; and

means for generating header information for the packet according to a packet header protocol from the different types of packet header data.

24. The device of claim 23, wherein the different types of packet header data include template data and layer 2 (L2) descriptor data.

25. The device of claim 24, wherein the different types of packet header data further include tag descriptor data.

26. The device of claim 23, wherein the packet header protocol is a layer 2 (L2) protocol.

27. A packet header processing engine comprising:

a memory including a plurality of distinct portions for respectively storing different types of descriptor information for a header of a packet; and

a packet header processing unit including a plurality of pointers corresponding to the plurality of distinct memory portions, the packet header processing unit being configured to retrieve the different types of descriptor information from the plurality of distinct memory portions and to generate header information from the different types of descriptor information.