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Processor with software-controlled programmable service levels

  • US 7,215,675 B2
  • Filed: 02/28/2002
  • Issued: 05/08/2007
  • Est. Priority Date: 02/28/2002
  • Status: Expired due to Fees
First Claim
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1. A processor comprising:

  • scheduling circuitry for scheduling data blocks for transmission from a plurality of transmission elements; and

    a priority computation element associated with the scheduling circuitry and operative to determine a transmission priority for one or more constituent transmission elements in a specified group of such transmission elements, the transmission priority being adjustable so as to facilitate the maintenance of a desired service level for one or more of the transmission elements;

    wherein the priority computation element determines a transmission priority for the constituent transmission elements of the group by designating one or more of the constituent transmission elements as current high priority transmission elements, with the other constituent transmission elements in the group being arranged in order of decreasing priority relative to the one or more current high priority transmission elements.

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