Device for WLAN baseband processing with DC offset reduction
First Claim
1. A baseband processor for processing an intermediate analogue signal received from a previous system, the baseband processor comprising:
- a programmable filter bank having a plurality of frequency pass characteristics and coupled to the previous system for filtering the intermediate analogue signal according to a filter state signal received from a filter state input and generating at an output a filtered signal;
an ADC (Analogue-to-Digital Converter) coupled to the output of the programmable filter bank for converting the filtered signal into a digital signal and generating at an output the digital signal;
a gain controller coupled to the output of the ADC for estimating a DC (Direct Current) offset of the digital signal and generating at a first output a gain control signal and at a second output a gain state signal, the gain control signal instructing the previous system to adjust a strength of the intermediate analogue signal;
a DC estimator coupled to the output of the ADC for estimating the DC offset of the digital signal and generating at a first output a first DC offset signal and at a second output a second DC offset signal corresponding to the DC offset;
a DAC (Digital-to-Analogue Converter) coupled to the first output of the DC estimator for receiving as an input the first DC offset signal and generating at an output a feedback signal corresponding to the first DC offset signal;
an arithmetic module coupled to the output of the DAC and to the output of the programmable filter bank, the arithmetic module subtracting the feedback signal from the filtered signal for canceling DC offsets of the programmable filter bank and the ADC; and
a DCF (DC-Filter) controller coupled to the second output of the DC estimator and to the second output of the gain controller for receiving the second DC offset signal to instruct the programmable filter bank having the plurality of the frequency pass characteristics to reduce DC offsets of the previous system, wherein the DCF controller receives the gain state signal and generates the filter state signal at an output, to which the filter state input of the programmable filter bank is coupled.
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Abstract
A device for processing an intermediate analogue signal received from a previous system with a baseband processor. The processor includes an ordinary feedback loop for adjusting the strength of the intermediate analogue signal received from the previous system. The processor further includes a first DC offset reduction loop and a second DC offset reduction loop. A programmable filter bank and the corresponding control elements are provided so that the second DC offset reduction loop can reduce the DC offset in a flexible way. In the present invention, the DC offset can be reduced effectively and the gain training period relating to the previous system and the baseband processor can be shortened.
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Citations
17 Claims
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1. A baseband processor for processing an intermediate analogue signal received from a previous system, the baseband processor comprising:
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a programmable filter bank having a plurality of frequency pass characteristics and coupled to the previous system for filtering the intermediate analogue signal according to a filter state signal received from a filter state input and generating at an output a filtered signal; an ADC (Analogue-to-Digital Converter) coupled to the output of the programmable filter bank for converting the filtered signal into a digital signal and generating at an output the digital signal; a gain controller coupled to the output of the ADC for estimating a DC (Direct Current) offset of the digital signal and generating at a first output a gain control signal and at a second output a gain state signal, the gain control signal instructing the previous system to adjust a strength of the intermediate analogue signal; a DC estimator coupled to the output of the ADC for estimating the DC offset of the digital signal and generating at a first output a first DC offset signal and at a second output a second DC offset signal corresponding to the DC offset; a DAC (Digital-to-Analogue Converter) coupled to the first output of the DC estimator for receiving as an input the first DC offset signal and generating at an output a feedback signal corresponding to the first DC offset signal; an arithmetic module coupled to the output of the DAC and to the output of the programmable filter bank, the arithmetic module subtracting the feedback signal from the filtered signal for canceling DC offsets of the programmable filter bank and the ADC; and a DCF (DC-Filter) controller coupled to the second output of the DC estimator and to the second output of the gain controller for receiving the second DC offset signal to instruct the programmable filter bank having the plurality of the frequency pass characteristics to reduce DC offsets of the previous system, wherein the DCF controller receives the gain state signal and generates the filter state signal at an output, to which the filter state input of the programmable filter bank is coupled. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. A baseband processor for processing an intermediate analogue signal received from a previous system, the baseband processor comprising:
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a programmable filter bank having a plurality of frequency pass characteristics and coupled to the previous system for filtering the intermediate analogue signal according to a filter state signal received from a filter state input and generating at an output a filtered signal; an ADC (Analogue-to-Digital Converter) coupled to the output of the programmable filter bank for converting the filtered signal into a digital signal and generating at an output the digital signal; a DC estimator coupled to the output of the ADC for estimating a DC offset of the digital signal and generating at a first output a first DC offset signal corresponding to the DC offset; and a DCF (DC-Filter) controller comprising a first input coupled to the first output of the DC estimator for receiving the first DC offset signal and generating a filter state signal at an output coupled to the filter state input for instructing the programmable filter bank having the plurality of the frequency pass characteristics to reduce DC offsets of the previous system. - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. An electronic device for processing an analogue signal received from a previous system, the electronic device comprising:
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a signal conversion loop for receiving the analogue signal and converting the analogue signal into a digital signal, the signal conversion loop comprising; a programmable filter bank having a plurality of frequency pass characteristics and coupled to the previous system for filtering the analogue signal according to a filter state signal received from a filter state input and generating at an output a filtered signal; and an ADC (Analogue-to-Digital Converter) coupled to the output of the programmable filter bank for converting the filtered signal into the digital signal; a digital demodulator for receiving and demodulating the digital signal; and a DC (direct current) offset reduction circuit coupled between the signal conversion loop and the digital demodulator and comprising a first DC reduction section for reducing a DC offset of the digital signal and a second DC reduction section for reducing a DC offset stemming from the previous system; wherein the first DC reduction section comprises; a DC estimator coupled to the output of the ADC for estimating a DC offset of the digital signal and generating at a first output a first DC offset signal and at a second output a second DC offset signal corresponding to the DC offset; a DAC (Digital-to-Analogue Converter) coupled to the first output of the DC estimator for receiving as an input the first DC offset signal and generating at an output a feedback signal corresponding to the first DC offset signal; and an arithmetic module coupled between the output of the programmable filter bank and the input of the ADC for receiving the feedback signal, the arithmetic module subtracting the feedback signal from the filtered signal for canceling the DC offset of the digital signal; wherein the second DC reduction section comprises; a DCF (DC-Filter) controller comprising a first input coupled to the second output of the DC estimator for receiving the second DC offset signal and generating a filter state signal at an output coupled to the filter state input for instructing the programmable filter bank having the plurality of the frequency pass characteristics to reduce DC offsets of the previous system; and a gain controller coupled to the output of the ADC for estimating a DC offset of the digital signal and generating at an output a gain control signal, the gain control signal instructing the previous system to adjust a strength of the analogue signal, the gain controller further comprising a receiver state input coupled to an output of the demodulator for receiving a receiver state signal.
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Specification