High throughout image for processing inspection images

• US 7,215,808 B2
• Filed: 06/02/2004
• Issued: 05/08/2007
• Est. Priority Date: 05/04/2004
• Status: Active Grant

• Current Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Original Assignee: Kla-Tencor Technologies Corporation (KLA Corporation)
• Inventors: Miller, Lawrence R.
• Primary Examiner(s): Bali; Vikkram
• Application Number:
  US10/860,617
• Publication Number:
  US 20050249395A1
• Time in Patent Office: 1,070 Days
• Field of Search: 382141-152, 712/20, 714/776
• US Class Current: 382/145
• CPC Class Codes: G01N 2021/95615 with stored comparision signal
• CPC Class Codes: G01N 2021/95676 Masks, reticles, shadow masks
• CPC Class Codes: G01N 21/9501 Semiconductor wafers manufacturing processes per se of semiconductor devices implementing a measuring step H01L22/10
• CPC Class Codes: G06T 2207/30148 Semiconductor; IC; Wafer
• CPC Class Codes: G06T 7/0004 Industrial image inspection

Abstract

Disclosed is an image processing system for analyzing images of a specimen to determine whether the specimen contains defects. The system includes a plurality of processors for receiving image data from a specimen and for analyzing one or more selected patch(es) of such image data to determine whether the specimen has a defect. The system also includes a plurality of buses for coupling the processors together, wherein the bus has the following specifications: a data rate of about 50 gigabits per second or more and an error rate less than about 10⁻¹⁶. In one implementation, the buses are low voltage differential signal type buses, and in another implementation, the buses are hyper transport type buses.

Claims

1. An image processing system for analyzing images of a specimen to determine whether the specimen contains defects, the system comprising:

a plurality of processors for receiving image data from a specimen and for at least a subset of the processors each analyzing one or more selected patch(es) of such image data to determine whether the specimen has a defect;

a plurality of buses for coupling the processors together, wherein one or more the bus(es) have the following specifications;

a high speed data rate of about 50 gigabits per second or more and an error rate less than about 10<sup>−

16</sup>, wherein the processors are distributed between at least two boards so as to allow the system to be scaled to include additional processors and wherein the one or more bus(es) that couple processors of two different boards have the high speed data rate; and

a clock module for generating a master clock for use by the processors and a pixel clock for defining pixels within the image data with respect to an angle clock of the inspection tool used for collecting the image data from the specimen, wherein the angle clock has a fixed number of pulses per a specific angle of rotation of the specimen, wherein the image data is collected from a rotating specimen and the pixel clock and synchronization signals are generated so that pixel resolution is altered according to a radial position of the specimen so as to obtain a substantially constant pixel resolution along the radius, wherein the synchronization signals indicate a relative position of the pixel clock with respect to the master clock.

2. A system as recited in claim 1, where the one or more bus(es) that have the high speed data rate are low voltage differential signal type buses.

3. A system as recited in claim 1, where the one or more bus(es) that have the high speed data rate are hyper transport type buses.

4. A system as recited in claim 1, wherein the processors are coupled together with the buses into a serial chain so that the processors sequentially receive the image data and analyze selected one or more patch(es) of such image data and wherein the processors are further operable to output one or more result signal(s) indicating whether the specimen has defects after analyzing their selected patch(es), wherein the result signal(s) of each processor are output with the image data.

5. A system as recited in claim 4, wherein the buses in the serial chain have the high speed data rate.

6. A system as recited in claim 5, wherein the buses in the serial chain are low voltage differential signal type buses.

7. A system as recited in claim 1, wherein the processors are arranged in a two level hierarchical arrangement so that one or more processors each referred to as a distributor are associated with a set of processors referred to as analyzing processors, wherein each distributor is operable to distribute a selected one or more patch(es) to each analyzing processor in its associated set for analysis of such distributed patch(es).

8. A system as recited in claim 7, wherein the distributors and their underlying analyzing processors are distributed between at least two boards so as to allow the system to be scaled to include additional distributors and their underlying analyzing processors and wherein the one or more bus(es) that couple the distributors together have the high speed data rate.

9. A system as recited in claim 7, wherein the processors include a single distributor for distributing one or more image patch(es) to each of a plurality of four associated analyzing processors, wherein each of the four analyzing processors receives a quarter of the image data from the specimen.

10. A system as recited in claim 7, wherein the processors include a first distributor for distributing one or more image patch(es) to each of a plurality of four associated analyzing processors for analysis of such distributed patch(es) and a second distributor for distributing one or more image patch(es) to each of a plurality of four associated analyzing processors for analysis of such distributed patch(es), wherein each of the eight analyzing processors receives an eighth of the image data from the specimen.

11. A system as recited in claim 10, further comprising a host for analyzing and or displaying defect data, wherein each analyzing processor is also operable to output one or more results signal(s) to the host, the result signal(s) indicating whether the specimen has a defect.

12. A system as recited in claim 1, wherein the image data corresponds to a plurality of semiconductor dies and wherein at least one or more of the processors are operable to generate a reference die based on an average of a portion of the dies of the image data and wherein one or more same or other processors are operable to compare the reference die to other dies in its image patch(es) to determine whether the specimen has a defect.

13. An image processing system for analyzing images of a specimen to determine whether the specimen contains defects, the system comprising:

a clock module for generating a master clock and a pixel clock;

a plurality of inspection signal processors for receiving different sets of optical signals obtained from an inspection tool while inspecting a specimen, wherein each inspection signal processor is operable to convert its received set of optical signals into digital image data and output such image data at a particular time slot of a the master clock sent to a next inspection signal processors if present, wherein the pixel clock is generated so as to define pixels within the image data with respect to an angle clock of the inspection tool used for collecting the image data from the specimen, wherein the angle clock has a fixed number of pulses per a specific angle of rotation of the specimen, wherein the image data is collected from a rotating specimen and the pixel clock and synchronization signals are generated so that pixel resolution is altered according to a radial position of the specimen so as to obtain a substantially constant pixel resolution along the radius, wherein the synchronization signals indicate a relative position of the pixel clock with respect to the master clock;

a distributor processor for receiving the image data from the plurality of inspection signal processors and for dividing the image data into a plurality of image patches; and

a plurality of analyzing processors associated with the distributor, wherein the distributor is further operable to distribute selected image patches to selected analyzing processors for parallel processing to determine whether the specimen has a defect, wherein the inspection signal processors are distributed among a plurality of boards so that there is at least one inspection signal processor per board and the signal processors are serially coupled together by a high speed bus having the following specifications;

a data rate of about 50 gigabits per second or more and an error rate less than about 10<sup>−

16</sup>.

14. A system as recited in claim 13, wherein the distributor receives the image data from a last one of the inspection signal processors after all of the inspection signal processors have contributed to the image data.

15. A system as recited in claim 14, wherein there are 12 inspection signal processors and eight analyzing processors.

16. A system as recited in claim 15, wherein there are two inspection signal processors per board, the distributor and associated analyzing processors are on a single board, and the inspection signal processors and the distributor are serially coupled together by a high speed bus having the following specifications:

a data rate of about 50 gigabits per second or more and an error rate less than about 10<sup>−

16</sup>.

17. A system as recited in claim 16, wherein the high speed bus is a low voltage differential signal type bus.

18. A system as recited in claim 13, wherein the analyzing processors are each further operable to send a signal to the inspection tool indicating that the inspection tool needs to decrease its image data output speed when the speed is greater than the each analyzing processor can process its image patch(es).

19. A system as recited in claim 13, wherein the optical signals are received in the form of annular swaths of the specimen.

20. A system as recited in claim 13, wherein the optical signals are received in the form of rectangular swaths of the specimen.