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Method and apparatus for solving an optimization problem in an integrated circuit layout

  • US 7,216,308 B2
  • Filed: 12/31/2002
  • Issued: 05/08/2007
  • Est. Priority Date: 11/18/2002
  • Status: Expired due to Fees
First Claim
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1. A method of solving an optimization problem that includes a plurality of elements in an integrated circuit (“

  • IC”

    ) layout, wherein one or more solutions are identified for each element in the plurality of elements, the method comprising;

    a) specifying a first solution set that has one identified solution for each element in the plurality of elements, wherein each element is a net in the IC layout;

    b) selecting a first element; and

    c) in the first solution set, replacing a current solution for the first element with another identified solution for the first element if the replacement would improve the first solution set.

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