Transistor fabrication methods using dual sidewall spacers
First Claim
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1. A method of fabricating a transistor, the method comprising:
- forming a gate structure over a channel region of a semiconductor body;
forming a first sidewall spacer along a lateral side of the gate structure;
forming a second sidewall spacer along a lateral side of the first sidewall spacer;
performing a deep source/drain implant to implant dopants into a source/drain region of the semiconductor body after forming the second sidewall spacer;
removing at least a portion of the second sidewall spacer after the deep source/drain implant; and
forming a stress inducing layer over the gate and the first sidewall spacer after removing at least a portion of the second sidewall spacer.
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Abstract
Methods (50) are presented for transistor fabrication, in which first and second sidewall spacers (120a, 120b) are formed laterally outward from a gate structure (114), after which a source/drain region (116) is implanted. The method (50) further comprises removing all or a portion of the second sidewall spacer (120b) after implanting the source/drain region (116), where the remaining sidewall spacer (120a) is narrower following the source/drain implant to improve source/drain contact resistance and PMD gap fill, and to facilitate inducing stress in the transistor channel.
36 Citations
21 Claims
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1. A method of fabricating a transistor, the method comprising:
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forming a gate structure over a channel region of a semiconductor body; forming a first sidewall spacer along a lateral side of the gate structure; forming a second sidewall spacer along a lateral side of the first sidewall spacer; performing a deep source/drain implant to implant dopants into a source/drain region of the semiconductor body after forming the second sidewall spacer; removing at least a portion of the second sidewall spacer after the deep source/drain implant; and forming a stress inducing layer over the gate and the first sidewall spacer after removing at least a portion of the second sidewall spacer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of fabricating a transistor, the method comprising:
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forming first and second sidewall spacers laterally outward from a gate structure, the first sidewall spacer extending between a lateral side of the gate structure and the second sidewall spacer; implanting a source/drain region of a semiconductor body after forming the first and second sidewall spacers; and removing substantially all of the second sidewall spacer after implanting the source/drain region; and forming a stress inducing layer over the gate and the first sidewall spacer after removing substantially all of the second sidewall spacer. - View Dependent Claims (16, 17, 18, 19, 20)
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21. A method of fabricating a transistor, the method comprising:
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forming a gate structure over a channel region of a semiconductor body; forming a first sidewall spacer along a lateral side of the gate structure, said forming including depositing SiWCXNY or SiWCXNYOZ using a BTBAS precursor; forming a second sidewall spacer along a lateral side of the first sidewall spacer, said forming a second sidewall spacer including depositing silicon nitride with substantially no carbon; performing a deep source/drain implant to implant dopants into a source/drain region of the semiconductor body after forming the second sidewall spacer; removing at least a portion of the second sidewall spacer after the deep source/drain implant; and forming a stress inducing layer over the gate and the first sidewall spacer after removing at least a portion of the second sidewall spacer.
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Specification