Technique for suppression of edge current in semiconductor devices

• US 7,217,953 B2
• Filed: 09/28/2004
• Issued: 05/15/2007
• Est. Priority Date: 04/20/2000
• Status: Expired due to Fees

• Current Assignee: Digirad Corporation
• Original Assignee: Digirad Corporation
• Inventors: Carlson, Lars S.
• Primary Examiner(s): Estrada; Michelle
• Assistant Examiner(s): Tobergte; Nicholas J.
• Application Number:
  US10/953,508
• Publication Number:
  US 20050173774A1
• Time in Patent Office: 959 Days
• Field of Search: 257/73, 257/233, 257/292, 257/E27.133, 257/E25.032, 438/92, 438/FOR.173
• US Class Current: 257/73
• CPC Class Codes: H01L 27/14601 Structural or functional details thereof
• CPC Class Codes: H01L 27/1463 Pixel isolation structures
• CPC Class Codes: H01L 27/1464 Back illuminated imager structures
• CPC Class Codes: H01L 27/14683 Processes or apparatus peculiar to the manufacture or treatment of these devices or parts thereof not peculiar thereto H01L21/00
• CPC Class Codes: H01L 27/14698 Post-treatment for the devices, e.g. annealing, impurity-gettering, shor-circuit elimination, recrystallisation
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 31/1121 Devices with Schottky gate
• CPC Class Codes: H01L 31/186 Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

A passive mechanism suppresses injection, into any active guard regions interposed between the edge of a photodiode array chip and the outer photodiode pixels or into the outer pixels themselves, of minority carrier current generated in the physically disrupted region at the edge of the semiconductor die created by cleaving, sawing or otherwise separating the chip from the remainder of the wafer on which the die was fabricated. A thin metallic layer covers all or part of the edge region, thereby creating a Schottky barrier. This barrier generates a depletion region in the adjacent semiconductor material. The depletion region inherently creates an energy band distribution which preferentially accelerates minority carriers generated or near the metal-semiconductor interface towards the metal, thereby suppressing collection of these carriers by any active regions of the guard structure or by the photodiode pixels.

Claims

1. A device, comprising:

A semiconductor substrate;

a gate region, in said semiconductor substrate, and having a gate structure to form a first depletion region in said semiconductor substrate adjacent said gate region, when biased;

an edge which is formed by dicing; and

an edge structure, coupled to said edge formed by dicing, and forming a second depletion region in an area of said edge formed by dicing.

2. A device as in claim 1, wherein said second depletion region formed by said edge structure is effective to prevent minority carriers from traveling to said first depletion region.

3. A device as in claim 1, wherein said structure includes a metal layer covering the edge formed by dicing.

4. A device as in claim 3, wherein said metal layer forms a Schottky barrier with the substrate.

5. A device as in claim 1, wherein said gate structure includes two spaced gates which form a continuous depletion region in an area adjacent to said two spaced gates.

6. A device as in claim 3, wherein said metal includes a bimetallic part.

7. A device as in claim 3, wherein said metal is a metal which forms a Schottky barrier height of at least 0.74 electron volts.

8. A device as in claim 1, further comprising structure in said semiconductor substrate forming a photodiode portion.

9. A device as in claim 8, wherein said structure forms an array of photodiodes.

10. A device as in claim 8, further comprising a rear biasing contact, formed on an opposite surface to a surface of said gate region.

11. A photo diode array, comprising:

a semiconductor substrate having at least one gate region on a first surface thereof, and a biasing electrode on a second opposite surface thereof, opposite to said first surface, said gate region and said biasing electrode being formed to create a depletion region near said gate region when biased by said biasing electrode, said semiconductor substrate also having at least one diced edge thereon; and

a second depletion layer forming region, coupled to said diced edge, and forming a second depletion region in an area near said diced edge, said second depletion region being effective to prevent minority carriers from said diced edge from traveling to said first depletion region.

12. A photo diode array as in claim 11, wherein said second depletion layer forming region includes a metal structure which is coupled to said diced edge.

13. A photo diode array as in claim 11, wherein said metal structure includes an intermetallic layer.

14. A photo diode array as in claim 11, wherein said metal structure is formed of a material from the group consisting of platinum or palladium.

15. A photo diode array as in claim 11, wherein said at least one gate region includes a plurality of gate regions which are spaced from one another, but which are effective to form a single first depletion region adjacent said plurality of the lawyers.

16. A photo diode array as in claim 11, wherein said second depletion layer forming region forms a Schottky barrier with the substrate.

17. A photo diode arrary as in claim 16, wherein said metal has a Schottky barrier height of at least 0.74 electron volts.