CMOS image sensor and method for manufacturing the same

• US 7,217,967 B2
• Filed: 12/23/2003
• Issued: 05/15/2007
• Est. Priority Date: 09/22/2003
• Status: Expired due to Fees

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: DONGBU ELECTRONICS CO., LTD. (DB HiTek Co., Ltd.)
• Inventors: Han, Chang Hun
• Primary Examiner(s): HOANG, QUOC DINH
• Application Number:
  US10/746,980
• Publication Number:
  US 20050064620A1
• Time in Patent Office: 1,239 Days
• Field of Search: 257/233, 257/292, 257/444, 257/463, 257/293
• US Class Current: 257/233
• CPC Class Codes: H01L 27/14603 Special geometry or disposition of pixel-elements, address-lines or gate-electrodes
• CPC Class Codes: H01L 27/14609 Pixel-elements with integrated switching, control, storage or amplification elements scanning details of imagers (circuitry of solid-state image sensors H04N25/00); circuitry of imagers H04N25/70
• CPC Class Codes: H01L 27/1463 Pixel isolation structures

Abstract

A CMOS image sensor and a manufacturing method thereof are disclosed. The gates of the transistors are formed in an active region of a unit pixel, and at the same time, a passivation layer is formed on an edge portion of the active region of a photodiode to have the same laminate structure as the gates of the transistors. Impurities for a diffusion region of the photodiode are ion-implanted into the active region for the photodiode, after the laminate structure is formed. The passivation layer prevents the edge portion from being damaged by ion implantation at the boundary or interface between the photodiode diffusion region and an isolation layer, which reduces dark current and/or leakage current of the CMOS image sensor.

Claims

1. A CMOS image sensor comprising:

a) a semiconductor substrate having an isolation region, an edge portion adjacent to the isolation region and an active region for a unit pixel, wherein the edge portion has width of 50 μ

m or more;

b) at least one transistor formed on said semiconductor substrate in said unit pixel;

c) a diffusion region for a photodiode, wherein the edge portion is between said diffusion region and said isolation region; and

d) an electrically isolated passivation layer on both the edge portion and a portion of the isolation region, but not on the diffusion region.

2. The CMOS image sensor as claimed in claim 1, wherein said transistor comprises a first layer and a second layer, wherein the first layer comprises a gate insulating material and the second layer comprises an electrode material.

3. The CMOS image sensor as claimed in claim 2, wherein said passivation layer comprises a first layer and a second layer, wherein the first layer comprises the same material as the gate insulating material of said transistor and the second layer comprises the same material as the electrode material of said transistor.

4. The CMOS image sensor as claimed in claim 3, wherein said first layer comprises a thermal oxide layer and said second layer comprises a polysilicon doped layer.

5. The CMOS image sensor as claimed in claim 4, wherein said second layer further comprises a silicide layer on said polysilicon layer.

6. The CMOS image sensor as claimed in claim 5, wherein the silicide layer comprises a material selected from a group consisting of tungsten silicide, molybdenum silicide and titanium silicide.

7. The CMOS image sensor as claimed in claim 3, wherein said transistor further comprises source/drain diffusion regions adjacent to said first and second layers of said transistor.

8. The CMOS image sensor as claimed in claim 1, wherein said isolation region comprises an isolation layer.

9. The CMOS image sensor as claimed in claim 8, wherein said isolation layer comprises a shallow trench isolation layer or LOCOS layer.

10. The CMOS image sensor as claimed in claim 1, wherein said semiconductor substrate comprises a P⁺⁺ type silicon substrate having a P⁻

type epitaxial layer thereon, and said diffusion region comprises an n⁻

type diffusion region.

11. The CMOS image sensor as claimed in claim 10, further comprising a P⁰ type diffusion region on said n⁻

if type diffusion region.

12. The CMOS image sensor as claimed in claim 1, wherein the edge portion has a medial edge aligned with a medial side of the passivation layer and lateral edge interfacing with the isolation region.

13. The CMOS image sensor as claimed in claim 1, wherein the substrate comprises single crystal silicon.

14. The CMOS image sensor as claimed in claim 1, wherein the edge portion is undoped.

15. A CMOS image sensor comprising:

a) a semiconductor substrate having a photodiode region having at least four sides, an isolation region along first, second and third sides of the photodiode region, and edge portions between each of the first, second and third sides of the photodiode region and the corresponding isolation region, wherein the edge portions have a width of 50 μ

m or more;

b) at least one transistor formed on said semiconductor substrate adjacent to a fourth side of the photodiode region; and

c) a passivation layer on both the edge portion and a portion of the isolation region along the first, second and third sides of the photodiode, but not on the photodiode region.

16. The CMOS image sensor as claimed in claim 15, further comprising a transfer transistor, a reset transistor, a driver transistor, and a select transistor.

17. The CMOS image sensor as claimed in claim 15, wherein the edge portion has a medial edge aligned with a medial side of the passivation layer and lateral interfacing with the isolation region.

18. The CMOS image sensor as claimed in claim 15, further comprising a diffusion region at the surface of the photodiode region, interfacing with the edge portion.

19. A CMOS image sensor comprising:

a) a semiconductor substrate having a photodiode region having at least four sides, an isolation region along first, second and third sides of the photodiode region, and edge portions between each of the first, second and third sides of the photodiode region and the corresponding isolation region;

b) at least one transistor formed on said semiconductor substrate adjacent to a fourth side of the photodiode region; and

a) an electrically isolated passivation layer on both the edge portion and a portion of the isolation region along the first, second and third sides of the photodiode, but not on the photodiode region.