Devices containing platinum-iridium films and methods of preparing such films and devices

• US 7,217,970 B2
• Filed: 08/06/2004
• Issued: 05/15/2007
• Est. Priority Date: 08/31/2000
• Status: Expired due to Fees

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Marsh, Eugene P.
• Primary Examiner(s): Pham; Thanhha S.
• Application Number:
  US10/912,906
• Publication Number:
  US 20050006689A1
• Time in Patent Office: 1,012 Days
• Field of Search: 257/296, 257/300, 257/301, 257/303, 257/306, 257/310
• US Class Current: 257/296
• CPC Class Codes: C23C 16/06 characterised by the deposition of metallic material
• CPC Class Codes: C23C 16/18 from metallo-organic compounds
• CPC Class Codes: H01L 21/28556 by chemical means, e.g. CVD, LPCVD, PECVD, laser CVD H01L21/28518 - H01L21/28537 and H01L21/28568 take precedence
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76864 Thermal treatment
• CPC Class Codes: H01L 21/7687 Thin films associated with contacts of capacitors
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665
• CPC Class Codes: H01L 28/65 comprising a noble metal or a noble metal oxide, e.g. platinum (Pt), ruthenium (Ru), ruthenium dioxide (RuO2), iridium (Ir), iridium dioxide (IrO2)

Abstract

Methods for forming platinum-iridium films, particularly in the manufacture of a semiconductor device, and devices (e.g., capacitors, integrated circuit devices, and memory cells) containing such films.

Claims

1. A capacitor comprising:

a semiconductor substrate or substrate assembly having a small high aspect ratio opening;

a silicon-containing conductive plug within the small high aspect ratio opening and recessed below a surface of the semiconductor substrate or substrate assembly;

a first platinum-iridium film directly on the silicon-containing conductive plug within the small high aspect ratio opening;

a dielectric material directly on at least a portion of the first platinum-iridium film; and

a second platinum-iridium film on the dielectric material, wherein at least the first platinum-iridium film is deposited by chemical vapor deposition or atomic layer deposition.

2. The capacitor of claim 1 wherein the at least one vapor-deposited platinum-iridium film has the formula platinum(x):

iridium(1−

x) wherein x is in the range of about 0.99 to about 0.01.

3. The capacitor of claim 2 wherein x is in the range of about 0.65 to about 0.85.

4. The capacitor of claim 3 wherein x is about 0.75.

5. The capacitor of claim 1 wherein the dielectric layer is selected from the group consisting of tantalum pentoxide, Barium Strontium Titanate, Strontium Titanate, Lead Zirconium Titanate, Strontium Bismuth Tantalate, and Bismuth Zirconium Titanate.

6. The capacitor of claim 1 wherein the silicon-containing conductive plug comprises a polysilicon.

7. The capacitor of claim 6 wherein the polysilicon comprises an arsenic or phosphorus doped polysilicon.

8. An integrated circuit comprising a capacitor, wherein the capacitor comprises:

a semiconductor substrate or substrate assembly having a small high aspect ratio opening;

a silicon-containing conductive plug within the small high aspect ratio opening and recessed below a surface of the semiconductor substrate or substrate assembly;

a first platinum-iridium film directly on the silicon-containing conductive plug within the small high aspect ratio opening;

a dielectric material directly on at least a portion of the first platinum-iridium film; and

a second platinum-iridium film on the dielectric material, wherein at least the first platinum-iridium film is deposited by chemical vapor deposition or atomic layer deposition.

9. The integrated circuit of claim 8 wherein the at least one vapor-deposited platinum-iridium film has the formula platinum(x):

iridium(1−

x), wherein x is in the range of about 0.99 to about 0.01.

10. The integrated circuit of claim 9 wherein x is in the range of about 0.65 to about 0.85.

11. The integrated circuit of claim 10 wherein x is about 0.75.

12. The integrated circuit of claim 8 wherein the dielectric layer is selected from the group consisting of tantalum pentoxide, Barium Strontium Titanate, Strontium Titanate, Lead Zirconium Titanate, Strontium Bismuth Tantalate, and Bismuth Zirconium Titanate.

13. The integrated circuit of claim 8 wherein the silicon-containing conductive plug comprises a polysilicon.

14. The integrated circuit of claim 13 wherein the polysilicon comprises an arsenic or phosphorus doped polysilicon.

15. A memory cell comprising a transistor and a capacitor, wherein the capacitor comprises:

a semiconductor substrate or substrate assembly having a small high aspect ratio opening;

a silicon-containing conductive plug within the small high aspect ratio opening and recessed below a surface of the semiconductor substrate or substrate assembly;

a first platinum-iridium film directly on the silicon-containing conductive plug within the small high aspect ratio opening;

a dielectric material directly on at least a portion of the first platinum-iridium film; and

a second platinum-iridium film on the dielectric material, wherein at least the first platinum-iridium film is deposited by chemical vapor deposition or atomic layer deposition.

16. The memory cell of claim 15 wherein the at least one vapor-deposited platinum-iridium film has the formula platinum(x):

iridium(1−

x), wherein x is in the range of about 0.99 to about 0.01.

17. The memory cell of claim 16 wherein x is in the range of about 0.65 to about 0.85.

18. The memory cell of claim 17 wherein x is about 0.75.

19. The memory cell of claim 15 wherein the dielectric layer is selected from the group consisting of tantalum pentoxide, Barium Strontium Titanate, Strontium Titanate, Lead Zirconium Titanate, Strontium Bismuth Tantalate, and Bismuth Zirconium Titanate.

20. The memory cell of claim 15 wherein the silicon-containing conductive plug comprises a polysilicon.

21. The memory cell of claim 20 wherein the polysilicon comprises an arsenic or phosphorus doped polysilicon.