Single and composite binary and multi-valued logic functions from gates and inverters
First Claim
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1. A ternary switch, comprising:
- an input that receives a ternary signal having one of three states;
an output that provides a ternary signal having one of three states;
and a control input;
wherein the input is connected to the output whenever the control input is in a first of three states.
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Abstract
Gates or switches for use in circuits implementing ternary and multi-value functions are disclosed. The gates can be optical, mechanical or electrical. The gates can conduct or not conduct when a control input assumes one of multiple states, or when a control input assumes two or more of multiple states. Circuits and methods for implementing ternary and multi-value functions are also disclosed. Corrective design techniques that can be used when a logic expression is incorrectly realized are also disclosed. Circuits that use inverters and gates to realize logic expressions are also provided.
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Citations
36 Claims
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1. A ternary switch, comprising:
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an input that receives a ternary signal having one of three states; an output that provides a ternary signal having one of three states; and a control input; wherein the input is connected to the output whenever the control input is in a first of three states. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. A method of switching a first ternary signal able to assume one of three states, from an input to an output under the control of a second ternary signal, comprising:
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conducting the first ternary signal on the input to the output whenever the second ternary signal is in a first of three states; and isolating the first ternary signal on the input from the output whenever the second ternary signal is in a second or a third of three states. - View Dependent Claims (9, 10, 11)
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12. A method of switching a first ternary signal from an input to an output under the control of a second ternary signal, comprising:
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conducting the first ternary signal on the input to the output whenever the second ternary signal is in a first or a second of three states; and isolating the first ternary signal on the input from the output whenever the second ternary signal is in a third of three states. - View Dependent Claims (13, 14, 15)
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16. A multi-value switch, comprising:
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an input that receives a signal able to assume one of x states, x being greater than or equal to four; an output that provides a signal able to assume one of x states, x being greater than or equal to four; and a control input; wherein the input is connected to the output whenever the control input is in a first of x states, x being greater than or equal to four. - View Dependent Claims (17, 18, 19, 20, 21, 22, 23)
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24. A method of switching a first multi-value signal from an input to an output under the control of a second multi-value signal, the first and second multi-value signals being able to assume one of x states wherein x is four or greater, comprising:
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conducting the first multi-value signal on the input to the output whenever the second multi-value signal is in a first of x states; and isolating the first multi-value signal on the input from the output whenever the second multi-value signal is not in the first of x states.
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25. A method of switching a first multi-value signal from an input to an output under the control of a second multi-value signal, the first and second multi-value signals being able to assume one of x states wherein x is four or greater, comprising:
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conducting the first multi-value signal on the input to the output whenever the second multi-value signal is in a first or a second of x states; and isolating the first multi-value signal on the input from the output whenever the second multi-value signal is not in the first or the second of x states.
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26. A method of switching a first multi-value signal from an input to an output under the control of a second multi-value signal, the first and second multi-value signals being able to assume one of x states wherein x is four or greater, comprising:
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conducting the first multi-value signal on the input to the output whenever the second multi-value signal is in a first or a second or a third of x states; and isolating the first multi-value signal on the input from the output whenever the second multi-value signal is not in the first or the second or third of x states.
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27. A circuit that expresses an n-valued logic equation having three or more n-valued variables and two or more n-valued logic functions, wherein n≧
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a fixed n-valued signal source; and a series and parallel connection of n-valued inverters and n-valued switches, the n-valued switches controlled by selected ones of the three or more n-valued variables in the n-valued equation, the series and parallel connection of n-valued inverters and n-valued switches having an input connected to the fixed n-valued signal source and an output.
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28. A circuit that expresses an n-valued logic equation on an output, the n-valued logic equation having three or more n-valued variables and two or more n-valued logic functions, wherein n≧
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an input connected to one of the three or more n-valued variable; and a series and parallel connection of n-valued inverters and n-valued switches, the n-valued switches controlled by selected ones of the three or more n-valued variables in the n-valued logic equation, the series and parallel connection of n-valued inverters and n-valued switches having an input connected to the one of the n-valued variable signal sources and the output.
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29. A circuit for processing a first ternary signal and a second ternary signal in accordance with a ternary logic function, comprising:
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a first input that can receive the first ternary signal; a second input that can receive the second ternary signal; an output; a first circuit connected between the first input and the output, the first circuit being enabled when the second ternary signal is in a first of three possible states, the first circuit outputting a value defined by the ternary logic function in accordance with the states of the first ternary signal and the second ternary signal; a second circuit connected between the first input and the output, the second circuit being enabled when the second ternary signal is in a second of three possible states, the second circuit outputting a value defined by the ternary logic function in accordance with the states of the first ternary signal and the second ternary signal; a third circuit connected between the first input and the output, the third circuit being enabled when the second ternary signal is in a third of three possible states, the third circuit outputting a value defined by the ternary logic function in accordance with the states of the first ternary signal and the second ternary signal. - View Dependent Claims (30)
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31. A method of processing a first ternary signal and a second ternary signal in accordance with a ternary logic function in an electronic circuit, comprising:
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inputting the first ternary signal and the second ternary signal to a first circuit, a second circuit and a third circuit; enabling the first circuit when the second ternary signal is in a first of three possible states, the first circuit outputting a value defined by the ternary logic function in accordance with the states of the first ternary signal and the second ternary signal; enabling the second circuit when the second ternary signal is in a second of three possible states, the second circuit outputting a value defined by the ternary logic function in accordance with the states of the first ternary signal and the second ternary signal; enabling the third circuit when the second ternary signal is in a third of three possible states, the third circuit outputting a value defined by the ternary logic function in accordance with the states of the first ternary signal and the second ternary signal. - View Dependent Claims (32)
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33. A circuit for processing a first multi-value signal and a second multi-value signal in accordance with a multi-value logic function, the first and second multi-value signals being able to assume one of x values wherein x is greater than or equal to four, comprising:
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a first input that can receive the first multi-value signal; a second input that can receive the second multi-value signal; an output; x circuits connected between the first input and the output, the first of the x circuits being enabled when the second multi-value signal is in a first of x possible states, the first circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal; the second of the x circuits being enabled when the second multi-value signal is in a second of x possible states, the second circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal; the third of the x circuits being enabled when the second multi-value signal is in a third of x possible states, the third circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal; the xth of x circuits being enabled when the second multi-value signal is in an xth of x possible states, the xth circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal. - View Dependent Claims (34)
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35. A method of processing a first multi-value signal and a second multi-value signal in accordance with a multi-value logic function in an electronic circuit, comprising:
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inputting the first multi-value signal and the second multi-value signal to x circuits; enabling a first of the x circuits when the second multi-value signal is in a first of x possible states, the first circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal; enabling a second of the x circuits when the second multi-value signal is in a second of x possible states, the second circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal; enabling a third of the x circuits when the second multi-value signal is in a third of x possible states, the third circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal; enabling an xth of the x circuits when the second multi-value signal is in an xth of x possible states, the xth circuit outputting a value defined by the multi-value logic function in accordance with the states of the first multi-value signal and the second multi-value signal. - View Dependent Claims (36)
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Specification