Domino logic with variable threshold voltage keeper

• US 7,218,151 B1
• Filed: 06/30/2003
• Issued: 05/15/2007
• Est. Priority Date: 06/28/2002
• Status: Expired due to Fees

• Current Assignee: University of Rochester
• Original Assignee: University of Rochester
• Inventors: Kursun, Volkan, Friedman, Eby G.
• Primary Examiner(s): Tran; Anh Q.
• Application Number:
  US10/608,421
• Time in Patent Office: 1,415 Days
• Field of Search: 326 93- 98
• US Class Current: 326/95
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence
• CPC Class Codes: H03K 2217/0018 Special modifications or use of the back gate voltage of a FET

Abstract

A variable threshold voltage keeper circuit technique is proposed for simultaneous power reduction and speed enhancement of domino logic circuits. The threshold voltage of the keeper transistor is dynamically modified during circuit operation to reduce the contention current without sacrificing noise immunity. The threshold voltage of the keeper transistor is controlled by a body bias generator which switches between two voltages in accordance with the clock signal.

Claims

1. A domino logic circuit comprising:

a pulldown circuit having a dynamic node;

a keeper connected to the pulldown circuit at the dynamic node; and

a source of a body bias voltage, the source of the body bias voltage being connected to the keeper to supply the body bias voltage to the keeper to bias the keeper;

wherein source supplies the body bias voltage such that the body bias voltage alternates between a first forward body bias voltage value and a second reverse body bias voltage value.

2. The domino logic circuit of claim 1, further comprising a foot transistor for connecting the pulldown circuit to ground.

3. The domino logic circuit of claim 1, wherein the pulldown circuit is connected to ground without an intervening foot transistor.

6. The domino logic circuit of claim 1, wherein the source supplies the body bias voltage such that the body bias voltage alternates between the first forward body bias voltage and the second reverse body bias voltage in accordance with a clock signal applied to the domino logic circuit.

4. A domino logic circuit comprising:

a pulldown circuit having a dynamic node;

a keeper connected to the pulldown circuit at the dynamic node; and

a source of a body bias voltage, the source of the body bias voltage being connected to the keeper to supply the body bias voltage to the keeper to bias the keeper;

wherein the body bias voltage is a reverse body bias voltage;

wherein the source supplies the reverse body bias voltage such that the reverse body bias voltage alternates between two values; and

wherein the source supplies the reverse body bias voltage such that the reverse body bias voltage alternates between the two values in accordance with a clock signal applied to the domino logic circuit.

5. A domino logic circuit comprising:

a pulldown circuit having a dynamic node;

a keeper connected to the pulldown circuit at the dynamic node; and

a source of a body bias voltage, the source of the body bias voltage being connected to the keeper to supply the body bias voltage to the keeper to bias the keeper;

wherein the source supplies the body bias voltage such that the body bias voltage alternates between two values; and

wherein the source supplies the body bias voltage such that the body bias voltage alternates between the two values in accordance with a clock signal applied to the domino logic circuit.

7. The domino logic circuit of claim 5, wherein the body bias voltage is a forward body bias voltage.