Techniques for controlling on-chip termination resistance using voltage range detection

• US 7,218,155 B1
• Filed: 01/20/2005
• Issued: 05/15/2007
• Est. Priority Date: 01/20/2005
• Status: Expired due to Fees

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Kim, Henry, Sung, Chiakang, Wang, Xiaobao, Nguyen, Khai Q., Chang, Tzung-Chin, Wang, Bonnie, Rangan, Gopinath, Tyhach, Jeffrey
• Primary Examiner(s): Callahan; Timothy P.
• Assistant Examiner(s): Nguyen; Hai L.
• Application Number:
  US11/040,343
• Time in Patent Office: 845 Days
• Field of Search: 327/306, 327/309, 327/108, 327/112, 326/30, 326/87
• US Class Current: 327/108
• CPC Class Codes: H03K 19/0005 Modifications of input or output impedance

Abstract

Techniques are provided for controlling an on-chip termination resistance in an input or output (IO) buffer using a calibration circuit. The calibration circuit monitors the voltage between an external resistor and a group of on-chip transistors. When voltage between the external resistor and the group of transistors is within a selected range, the calibration circuit causes the effective resistance of the transistors to match the resistance of the external resistor as closely as possible. The calibration circuit enables another set of transistors in the IO buffer so that the effective on resistance of the transistors in the IO buffer closely match the resistance of the external resistor.

Claims

1. An integrated circuit comprising a calibration circuit that controls a termination resistance in a buffer coupled to a first pin, the calibration circuit comprising:

first transistors; and

a control circuit coupled to the first transistors that monitors an effective resistance of the first transistors and that selectively enables a set of the first transistors using control signals generated by a counter circuit, the control circuit selecting values of the control signals corresponding to the effective resistance of the first transistors that is nearest to a resistance value, wherein the selected control signals are used to control a termination resistance of second transistors in the buffer,

wherein the control circuit comprises;

a first comparator coupled to monitor a voltage across the first transistors, wherein the counter circuit is coupled to monitor an output signal of the first comparator;

a first storage circuit coupled to receive the control signals generated by the counter circuit;

second and third comparators coupled to monitor the voltage across the first transistors; and

a logic gate coupled to receive output signals of the second and the third comparators, an output signal of the logic gate indicating when the voltage across the first transistors is within a selected voltage range.

2. The integrated circuit defined in claim 1 wherein the first transistors are coupled to a second pin, and the resistance value is a resistance of an external resistor coupled to the second pin.

3. The integrated circuit defined in claim 1 wherein the control circuit further comprises:

a pattern detect circuit coupled to receive the output signal of the first comparator, wherein an input of the first storage circuit is coupled to receive an output signal of the pattern detect circuit.

4. The integrated circuit defined in claim 1 wherein the first comparator has an enable input coupled to an enable signal, the enable signal causing current reduction in the first comparator during a stable calibration state.

5. The integrated circuit defined in claim 1 wherein the control circuit further comprises:

a second storage circuit coupled to receive the output signal of the logic gate and the control signals generated by the counter circuit; and

a pattern detect circuit coupled to receive the output signal of the logic gate.

6. The integrated circuit defined in claim 5 wherein the control circuit further comprises:

a multiplexer having inputs coupled to receive output signals of the first storage circuit and the second storage circuit, the multiplexer having a select input coupled to receive an output signal of the pattern detect circuit.

7. An integrated circuit comprising a calibration circuit that controls a termination resistance in a buffer coupled to a first pin, the calibration circuit comprising:

first transistors;

a control circuit coupled to the first transistors that monitors an effective resistance of the first transistors and that selectively enables a set of the first transistors using control signals generated by a counter circuit, the control circuit selecting values of the control signals corresponding to the effective resistance of the first transistors that is nearest to a resistance value, wherein the selected control signals are used to control a termination resistance of second transistors in the buffer; and

a multiplexer having an output coupled to the first transistors and inputs coupled to the counter circuit and a ground voltage, the multiplexer causing the first transistors to be off during a stable calibration state.

8. An integrated circuit comprising a calibration circuit that controls a termination resistance in a buffer coupled to a first pin, the calibration circuit comprising:

first transistors;

a control circuit coupled to the first transistors that monitors an effective resistance of the first transistors and that selectively enables a set of the first transistors using control signals generated by a counter circuit, the control circuit selecting values of the control signals corresponding to the effective resistance of the first transistors that is nearest to a resistance value, wherein the selected control signals are used to control a termination resistance of second transistors in the buffer; and

a multiplexer having an output coupled to the first transistors and inputs coupled to the counter circuit and user setting signals, the multiplexer causing the first transistors to be coupled to receive the user setting signals during a stable calibration state.

9. An integrated circuit having a calibration circuit that controls a termination resistance of a buffer coupled to a first pin of the integrated circuit, the calibration circuit comprising:

first transistors;

a first comparator coupled to compare a voltage across the first transistors with a first reference voltage;

a transistor control circuit coupled to receive an output of the first comparator and generating control signals that selectively enable the first transistors; and

a voltage range detection circuit coupled to determine whether a voltage across the first transistors falls within a voltage range,

wherein the voltage range detection circuit transmits values of the control signals to the buffer that cause the voltage across the first transistors to fall within the voltage range.

10. The integrated circuit defined in claim 9 wherein the first transistors are coupled to a second pin, and an external resistor is coupled to the second pin.

11. The integrated circuit defined in claim 9 wherein the transistor control circuit comprises a counter circuit that generates the control signals in response to an output signal of the first comparator, and wherein the control signals are count signals.

12. The integrated circuit defined in claim 11 wherein the transistor control circuit further comprises a first register coupled to receive the count signals, and a first pattern detect circuit coupled to receive the output signal of the first comparator and coupled to an input of the first register.

13. The integrated circuit defined in claim 12 wherein the voltage range detection circuit comprises a second comparator coupled to a second reference voltage and a third comparator coupled to a third reference voltage, the second and the third reference voltages defining the voltage range.

14. The integrated circuit defined in claim 13 wherein the voltage range detection circuit further comprises a second register coupled to receive the count signals, and a second pattern detect circuit coupled to receive an output signal generated by the second and third comparators, and wherein an input of the second register is coupled to receive the output signal generated by the second and third comparators.

15. The integrated circuit defined in claim 14 wherein the voltage range detection circuit further comprises a multiplexer coupled to receive output signals of the first and second registers and an output signal of the second pattern detect circuit.

16. The integrated circuit defined in claim 14 wherein an output voltage of the second pattern detect circuit changes states when an output of the second and third comparators makes at least three high-to-low or low-to-high transitions.

17. An integrated circuit comprising a calibration circuit that controls a termination resistance in a buffer coupled to a first pin, the calibration circuit comprising:

first transistors coupled to a second pin;

a first comparator having a first input coupled to the first transistors;

a counter circuit coupled to receive an output signal of the first comparator, wherein count signals generated by the counter circuit selectively enable the first transistors;

a first storage circuit coupled to receive the count signals;

second and third comparators having inputs coupled to the first transistors;

a second storage circuit coupled to receive an output signal of the second and third comparators and the count signals; and

a multiplexer that selects a set of control signals stored in one of the first and the second storage circuits and provides the selected control signals to the buffer to select the termination resistance.

18. The integrated circuit according to claim 17 wherein the second and third comparators detect when a voltage across the first transistors is within a voltage range indicating an effective resistance of the first transistors is closest to a resistance of an external resistor coupled to the second pin.

19. The integrated circuit according to claim 18 wherein the multiplexer selects control signals stored in the second storage circuit when a pattern detect circuit detects that the output signal of the second and third comparators is toggling.

20. A method for controlling a termination resistance of a buffer coupled to a first pin of an integrated circuit, the method comprising:

comparing a voltage across first transistors to a first reference voltage using a first comparator;

generating control signals that selectively enable the first transistors;

comparing a voltage across the first transistors to second and third reference voltages using second and third comparators;

storing the control signals in a first storage circuit when an output signal of the first comparator changes state;

storing the control signals in a second storage circuit when the voltage across the first transistors falls between the second and third reference voltages; and

selectively coupling the control signals stored in the first and the second storage circuits to the buffer to control the termination resistance.

21. The integrated circuit according to claim 20 wherein selectively coupling the control signals to the buffer further comprises selecting the control signals stored in the second storage circuit to control the termination resistance of second transistors in the buffer when a pattern detect circuit detects that an output signal of the second and third comparators toggles between high and low values.

22. The integrated circuit according to claim 20 further comprising:

turning off the first transistors and disabling the first comparator in a stable calibration state.

23. The integrated circuit according to claim 20 further comprising:

selectively coupling user setting signals to gates of the first transistors in a user mode.