Apparatus and method for memory operations using address-dependent conditions
First Claim
Patent Images
1. An apparatus comprising:
- a plurality of word lines and word line drivers;
a plurality of bit lines and bit line drivers;
a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and
circuitry operative to select a writing condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver;
wherein the circuitry is operative to select a different writing condition to apply to memory cells that are closer to the one or both of a word line driver and a bit line driver than to memory cells that are farther from the one or both of a word line driver and a bit line driver.
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Abstract
An apparatus is disclosed comprising a plurality of word lines and word line drivers, a plurality of bit lines and bit line drivers, and a plurality of memory cells coupled between respective word lines and bit lines. The apparatus also comprises circuitry operative to select a writing and/or reading condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver. The apparatus can also comprise circuitry that is operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to a word line and/or bit line driver.
120 Citations
45 Claims
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1. An apparatus comprising:
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a plurality of word lines and word line drivers; a plurality of bit lines and bit line drivers; a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and circuitry operative to select a writing condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver; wherein the circuitry is operative to select a different writing condition to apply to memory cells that are closer to the one or both of a word line driver and a bit line driver than to memory cells that are farther from the one or both of a word line driver and a bit line driver. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15)
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16. An apparatus comprising:
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a plurality of word lines and word line drivers; a plurality of bit lines and bit line drivers; a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and circuitry operative to select a writing condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver; wherein the writing condition comprises a voltage, and wherein the circuitry selects less of a voltage to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.
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17. An apparatus comprising:
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a plurality of word lines and word line drivers; a plurality of bit lines and bit line drivers; a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and circuitry operative to select a writing condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver; wherein the writing condition comprises a reference current, and wherein the circuitry selects a greater reference current to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.
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18. An apparatus comprising:
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a plurality of word lines and word line drivers; a plurality of bit lines and bit line drivers; a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and circuitry operative to select a writing condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver; wherein the writing condition comprises both a voltage and a reference current, wherein the circuitry selects less voltage and a greater reference current to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.
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19. An apparatus comprising:
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a plurality of word lines and word line drivers; a plurality of bit lines and bit line drivers; a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and circuitry operative to select a reading condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver; wherein the circuitry is operative to select a different reading condition to apply to memory cells that are closer to the one or both of a word line driver and a bit line driver than to memory cells that are farther from the one or both of a word line driver and a bit line driver. - View Dependent Claims (20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32)
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33. An apparatus comprising:
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a plurality of word lines and word line drivers; a plurality of bit lines and bit line drivers; a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and circuitry operative to select a reading condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver; wherein the reading condition comprises a voltage, and wherein the circuitry selects less of a voltage to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.
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34. An apparatus comprising:
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a plurality of word lines and word line drivers; a plurality of bit lines and bit line drivers; a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and circuitry operative to select a reading condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver; wherein the reading condition comprises a reference current, and wherein the circuitry selects a greater reference current to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.
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35. An apparatus comprising:
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a plurality of word lines and word line drivers; a plurality of bit lines and bit line drivers; a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and circuitry operative to select a reading condition to apply to a memory cell based on the memory cell'"'"'s location with respect to one or both of a word line driver and a bit line driver; wherein the reading condition comprises both a voltage and a reference current, wherein the circuitry select less of a voltage and a greater reference current to apply to memory cells closer to the one or both of a word line driver and a bit line driver than to memory cells farther from the one or both of a word line driver and a bit line driver.
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36. An apparatus comprising:
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a plurality of word lines and word line drivers; a plurality of bit lines and bit line drivers; a plurality of memory cells, wherein each memory cell is coupled between a respective word line and bit line; and circuitry operative to select a number of memory cells to be programmed in parallel based on memory cell location with respect to one or both of a word line driver and a bit line driver; wherein the circuitry is operative to select a different number of memory cells to be programmed in parallel for memory cells that are closer to the one or both of a word line driver and a bit line driver than for memory cells that are farther from the one or both of a word line driver and a bit line driver. - View Dependent Claims (37, 38, 39, 40, 41, 42, 43, 44, 45)
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Specification