H2 plasma treatment

• US 7,220,665 B2
• Filed: 08/05/2003
• Issued: 05/22/2007
• Est. Priority Date: 08/05/2003
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Farrar, Paul A.
• Primary Examiner(s): Kebede; Brook
• Application Number:
  US10/634,274
• Publication Number:
  US 20050032352A1
• Time in Patent Office: 1,386 Days
• Field of Search: 438/618, 438/619, 438622-629, 438/648, 438/650, 438/654, 438/656, 438/675, 438/678, 438683-687, 438/642, 438/584, 257/E23.145, 257/E23.142, 257/E23.154, 257/E21.575, 257/E21.576, 257/E21.584, 257/E21.577
• US Class Current: 438/622
• CPC Class Codes: H01L 21/76801 characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
• CPC Class Codes: H01L 21/7682 the dielectric comprising air gaps
• CPC Class Codes: H01L 21/76825 by exposing the layer to particle radiation, e.g. ion implantation, irradiation with UV light or electrons etc. plasma treatment H01L21/76826
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76849 the layer being positioned on top of the main fill metal
• CPC Class Codes: H01L 21/76859 by ion implantation
• CPC Class Codes: H01L 21/76867 characterized by methods of formation other than PVD, CVD or deposition from a liquids PVD H01L21/2855; CVD H01L21/28556; deposition from liquids H01L21/288
• CPC Class Codes: H01L 21/76873 for electroplating
• CPC Class Codes: H01L 21/76874 for electroless plating
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288

Abstract

Electronic devices are constructed by a method that includes forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, forming a core conductive layer on the first conductive layer, subjecting the core conductive layer to a H₂ plasma treatment, and depositing a capping adhesion/barrier layer on the core conductive layer after the H₂ plasma treatment. The multilayer dielectric structure provides an insulating layer for around the core conducting layer and at least one sacrificial layer for processing. The H₂ plasma treatment removes unwanted oxide from the surface region of the core conducting layer such that the interface between the core conducting layer and the capping adhesion/barrier is substantially free of oxides. In an embodiment, the core conducting layer is copper with a titanium nitride or zirconium capping adhesion/barrier layer.

Claims

1. A method for forming an electronic device comprising:

forming a first conductive layer in an opening in a dielectric structure supported by a substrate, the first conductive layer being an adhesion/barrier layer;

depositing a seed layer on the first conductive layer;

forming a core conductive layer on the seed layer, the core conductive layer substantially including one or more of aluminum, silver, or gold;

subjecting the core conductive layer to a H₂ plasma treatment; and

depositing a capping layer on the core conductive layer after the H₂ plasma treatment.

2. The method of claim 1, wherein forming the first conductive layer includes forming a layer of a refractory metal.

3. The method of claim 1, wherein forming the first conductive layer includes forming a layer of a compound of nitrogen and a tantalum alloy or a compound of nitrogen and a tungsten alloy.

4. The method of claim 1, wherein depositing the seed layer and the capping layer includes depositing the seed layer and the capping layer using low energy ion implantation.

5. The method of claim 4, wherein depositing the seed layer and the capping layer using low energy ion implantation includes using an implant energy ranging from about 0.1 keV to about 2 keV.

6. The method of claim 1, wherein forming the core conductive layer includes depositing the core conductive layer using a CVD process.

7. The method of claim 1, wherein forming the core conductive layer includes forming the core conductive layer at a temperature ranging from room temperature to about 250°

C.

8. The method of claim 1, wherein depositing the capping layer includes depositing one or more materials selected from titanium, zirconium, hafnium, or nitrides of these elements.

9. The method of claim 1, wherein depositing the capping layer includes depositing the capping layer having a thickness ranging from about 5 Å

to about 40 Å

.

10. The method of claim 1, wherein the method further includes removing at least a portion of the dielectric structure, after depositing the capping layer on the core conductive layer, to form an air bridge structure.

11. The method of claim 1, wherein forming the first conductive layer includes forming the first conductive layer in the dielectric structure having multiple dielectrics layers, such that the core conductive layer is within one dielectric layer in the dielectric structure.

12. The method of claim 11, wherein forming the first conductive layer in the dielectric structure having multiple dielectrics layers includes forming the first conductive layer within an opening in a polymer layer, a foamed polymer layer, a fluorinated polymer layer, a fluorinated oxide layer, or an aerogel layer.

58. The method of claim 1, wherein the method includes forming the electronic device configured as an integrated circuit.

59. The method of claim 1, wherein the method includes forming the electronic device configured as a memory device.

60. The method of claim 1, wherein the method includes forming the electronic device configured as part of an electronic system.

13. A method for forming an integrated circuit comprising:

forming one or more device structures on a substrate;

forming a polyimide layer above a number of first level vias provided for electrical coupling to at least one of the one or more device structures;

forming a number of trenches in the polyimide layer;

forming a first conductive layer in the number of trenches, the first conductive layer being an adhesion/barrier layer;

depositing a seed layer on the first conductive layer;

depositing a core conductive layer on the seed layer, the core conductive layer substantially including one or more of aluminum, silver, or gold;

subjecting the core conductive layer to a H₂ plasma treatment; and

depositing a capping layer on the conductive layer after the H₂ plasma treatment.

14. The method of claim 13, wherein forming the first conductive layer includes forming a layer of a refractory metal.

15. The method of claim 13, wherein forming the first conductive layer includes forming a layer of a compound of nitrogen and a tantalum alloy or a compound of nitrogen and a tungsten alloy.

16. The method of claim 13, wherein depositing the capping layer includes depositing material by ion implantation into the core conductive layer to form the capping layer.

17. The method of claim 13, wherein depositing the capping layer includes depositing one or more materials selected from titanium, zirconium, hafnium, or nitrides of these elements.

18. The method of claim 13, wherein forming the polyimide layer above a number of first level vias includes:

forming a field oxide layer and a Si₃N₄ layer above the one or more device structures;

forming contact holes through the field oxide layer and the Si₃N₄ layer;

depositing TiN in the contact holes;

forming tungsten on the TiN to form a contact plug; and

applying the polyimide on the Si₃N₄ layer and contact plug.

19. The method of claim 13, wherein forming the number of trenches in the polyimide layer includes:

forming an oxide layer on the polyimide layer;

forming a layer of Si₃N₄ on the oxide layer;

forming a damascene image in the oxide and Si₃N₄ layers; and

removing polyimide at locations of the damascene image.

20. The method of claim 19, wherein the method further including removing the layer of Si₃N₄ using a selective etch after forming the first conductive layer, and after depositing the capping layer subjecting the oxide layer to an etchant that removes the oxide layer without substantially altering the polyimide layer.

21. The method of claim 13, wherein depositing the core conductive layer includes selectively depositing aluminum.

22. The method of claim 13, wherein depositing the core conductive layer includes selectively depositing aluminum by plating in an ambient air environment.

23. The method of claim 13, wherein depositing the capping layer on the core conductive layer includes implanting zirconium ions into the core conductive layer.

24. The method of claim 13, wherein forming the polyimide layer includes forming a foamed polyimide, a fluorinated polyimide, or a foamed fluorinated polyimide.

25. The method of claim 13, wherein the method further includes a heat treatment at a temperature ranging from 250°

C. to about 350°

C. for a period ranging from about one hour to about two hours after depositing the capping layer on the core conductive layer.

26. The method of claim 13, wherein the method further includes removing at least a portion of the polyimide layer, after depositing the capping layer on the core conductive layer, to form an air bridge structure.

27. A method for forming an integrated circuit comprising:

forming one or more device structures on a substrate;

forming a first oxide layer above a number of first level vias for electrical coupling to at least one of the one or more device structures;

forming a number of trenches in the first oxide layer;

forming a first conductive layer in the number of trenches, the first conductive layer being an adhesion/barrier layer;

depositing a seed layer on the first conductive layer;

depositing a core conductive layer on the seed layer, the core conductive layer substantially including one or more of aluminum, silver, or gold;

subjecting the core conductive layer to a H₂ plasma treatment; and

depositing a capping layer on the core conductive layer after the H₂ plasma treatment.

28. The method of claim 27, wherein forming the first conductive layer includes forming a layer of a refractory metal.

29. The method of claim 27, wherein forming the first conductive layer includes forming a layer of a compound of nitrogen and a tantalum alloy or a compound of nitrogen and a tungsten alloy.

30. The method of claim 27, wherein depositing the capping layer includes depositing material by ion implantation into the core conductive layer to form the capping layer.

31. The method of claim 27, wherein depositing the capping layer includes depositing one or more materials selected from titanium, zirconium, hafnium, or nitrides of these elements.

32. The method of claim 27, wherein forming the first oxide layer above the device structures includes:

forming a field oxide layer and a Si₃N₄ layer above the one or more device structures;

forming contact holes through the field oxide layer and the Si₃N₄ layer;

depositing TiN in the contact holes;

forming tungsten on the TiN to form a contact plug; and

forming the first oxide layer on the Si₃N₄ layer and contact plug.

33. The method of claim 27, wherein forming the number of trenches in the first oxide layer includes:

forming a layer of Si₃N₄ on the first oxide layer;

applying a layer of resist;

forming a damascene image in the resist and Si₃N₄ layers; and

applying an oxide etch to define the number of trenches in the first oxide layer at locations of the damascene image.

34. The method of claim 33, wherein the method further includes after forming the first conductive layer removing the resist layer by a selective etch such that the first oxide layer is essentially unaltered by the selective etch.

35. The method of claim 27, wherein depositing the core conductive layer includes selectively depositing aluminum.

36. The method of claim 27, wherein depositing the core conductive layer includes selectively depositing aluminum by plating in an ambient air environment.

37. The method of claim 27, wherein depositing the capping layer on the core conductive layer includes implanting titanium ions into the core conductive layer.

38. The method of claim 37, wherein the method further includes exposing the titanium to nitrogen to form TiN.

39. The method of claim 27, wherein the method further includes removing at least a portion of the first oxide layer, after depositing the capping layer on the core conductive layer, to form an air bridge structure.

40. A method of forming a memory device comprising:

forming an array of memory cells in a substrate; and

forming a wiring structure in the substrate coupling to the array of memory cells, at least a portion of the wiring structure formed by a method including;

forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, the first conductive layer being an adhesion/barrier layer;

depositing a seed layer on the first conductive layer;

forming a core conductive layer on the seed layer, the core conductive layer substantially including one or more of aluminum, silver, or gold;

subjecting the core conductive layer to a H₂ plasma treatment; and

depositing a capping layer on the core conductive layer after the H₂ plasma treatment, the capping layer being a conductive adhesion/barrier layer.

41. The method of claim 40, wherein forming the first conductive layer includes forming a layer of a refractory metal.

42. The method of claim 40, wherein forming the first conductive layer includes forming a layer of a compound of nitrogen and a tantalum alloy or a compound of nitrogen and a tungsten alloy.

43. The method of claim 40, wherein forming the core conductive layer includes forming the core conductive layer at a temperature ranging from room temperature to about 250°

C.

44. The method of claim 40, wherein depositing the capping layer includes depositing one or more materials selected from titanium, zirconium, hafnium, or nitrides of these elements.

45. The method of claim 40, wherein depositing the capping layer includes depositing the capping layer having a thickness ranging from about 5 Å

to about 40 Å

.

46. The method of claim 40, wherein forming the core conductive layer includes forming the core conductive layer in the opening in the multilayer dielectric structure such that the core conductive layer is within one dielectric layer in the multilayer dielectric structure.

47. The method of claim 46, wherein forming the core conductive layer within one dielectric layer includes forming the core conductive layer within a polymer layer, a foamed polymer layer, a fluorinated polymer layer, an oxide layer, a silicon oxide layer, a fluorinated oxide layer, or an aerogel layer.

48. A method of forming an electronic system comprising:

providing a controller;

coupling the controller to one or more integrated circuits, at least the controller or one integrated circuit having a wiring structure on a substrate, at least a portion of the wiring structure formed by a method including;

forming a first conductive layer in an opening in a multilayer dielectric structure supported by a substrate, the first conductive layer being an adhesion/barrier layer;

depositing a seed layer on the first conductive layer;

forming a core conductive layer on the seed layer, the core conductive layer substantially including one or more of aluminum, silver, or gold;

subjecting the core conductive layer to a H₂ plasma treatment; and

depositing a capping layer on the core conductive layer after the H₂ plasma.

49. The method of claim 48, wherein forming the first conductive layer includes forming a layer of a refractory metal.

50. The method of claim 48, wherein forming the first conductive layer includes forming a layer of a compound of nitrogen and a tantalum alloy or a compound of nitrogen and a tungsten alloy.

51. The method of claim 48, wherein forming the core conductive layer includes forming the core conductive layer at a temperature ranging from room temperature to about 250°

C.

52. The method of claim 48, wherein depositing the capping layer includes depositing one or more materials selected from titanium, zirconium, hafnium, or nitrides of these elements.

53. The method of claim 48, wherein depositing the capping layer includes depositing the capping layer having a thickness ranging from about 5 Å

to about 40 Å

.

54. The method of claim 48, wherein forming the core conductive layer includes forming the core conductive layer in the opening in the multilayer dielectric structure such that the core conductive layer is within one dielectric layer in the multilayer dielectric structure.

55. The method of claim 54, wherein forming the core conductive layer within one dielectric layer includes forming the core conductive layer within a polymer layer, a foamed polymer layer, a fluorinated polymer layer, an oxide layer, a silicon oxide layer, a fluorinated oxide layer, or an aerogel layer.

56. The method of claim 48, wherein providing the controller includes providing a processor.

57. The method of claim 48, wherein forming the electronic system includes providing a computer.