Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors
First Claim
Patent Images
1. A silicon carbide metal-oxide semiconductor field effect transistor unit cell, comprising:
- an n-type silicon carbide drift layer;
a first p-type silicon carbide region in close proximity to the drift layer;
a first n-type silicon carbide region within the first p-type silicon carbide region;
an oxide layer on the drift layer, the first p-type silicon carbide region, and the first n-type silicon carbide region; and
an n-type silicon carbide limiting region disposed between the drift layer and the first p-type silicon carbide region, wherein the n-type limiting region comprises a first portion disposed in close proximity to a floor of the first p-type silicon carbide region and a second portion disposed in close proximity to a sidewall of the first p-type silicon carbide region, wherein the n-type limiting region has a carrier concentration that is greater than a carrier concentration of the drift layer and wherein the first portion has a carrier concentration greater than a carrier concentration of the second portion.
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Abstract
Silicon carbide metal-oxide semiconductor field effect transistors (MOSFETs) may include an n-type silicon carbide drift layer, a first p-type silicon carbide region adjacent the drift layer and having a first n-type silicon carbide region therein, an oxide layer on the drift layer, and an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type region. The limiting region may have a carrier concentration that is greater than the carrier concentration of the drift layer. Methods of fabricating silicon carbide MOSFET devices are also provided.
152 Citations
25 Claims
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1. A silicon carbide metal-oxide semiconductor field effect transistor unit cell, comprising:
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an n-type silicon carbide drift layer; a first p-type silicon carbide region in close proximity to the drift layer; a first n-type silicon carbide region within the first p-type silicon carbide region; an oxide layer on the drift layer, the first p-type silicon carbide region, and the first n-type silicon carbide region; and an n-type silicon carbide limiting region disposed between the drift layer and the first p-type silicon carbide region, wherein the n-type limiting region comprises a first portion disposed in close proximity to a floor of the first p-type silicon carbide region and a second portion disposed in close proximity to a sidewall of the first p-type silicon carbide region, wherein the n-type limiting region has a carrier concentration that is greater than a carrier concentration of the drift layer and wherein the first portion has a carrier concentration greater than a carrier concentration of the second portion. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A silicon carbide metal-oxide semiconductor field effect transistor unit cell, comprising:
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an n-type silicon carbide drift layer; a first p-type silicon carbide region adjacent the drift layer; a first n-type silicon carbide region within the first p-type silicon carbide region; an oxide layer on the drift layer, the first p-type silicon carbide region, and the first n-type silicon carbide region; an n-type silicon carbide limiting region disposed between the drift layer and a portion of the first p-type silicon carbide region, wherein the n-type limiting region has a carrier concentration that is greater than a carrier concentration of the drift layer; and an n-type epitaxial layer on the first p-type silicon carbide region and a portion of the first n-type region, and disposed between the first n-type silicon carbide region and the first p-type silicon carbide region and the oxide layer.
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12. A silicon carbide metal-oxide semiconductor field effect transistor, comprising:
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a drift layer of n-type silicon carbide;
first regions of p-type silicon carbide in close proximity to the drift layer;a first region of n-type silicon carbide disposed between peripheral edges of the first regions of p-type silicon carbide; second regions of n-type silicon carbide within the first regions of p-type silicon carbide, wherein the second regions of n-type silicon carbide have a carrier concentration greater than a carrier concentration of the drift layer and are spaced apart from the peripheral edges of the first regions of p-type silicon carbide; an oxide layer on the drift layer, the first region of n-type silicon carbide and the second regions of n-type silicon carbide; third regions of n-type silicon carbide disposed beneath the first regions of p-type silicon carbide and between the first regions of p-type silicon carbide and the drift layer, wherein the third regions of n-type silicon carbide have a carrier concentration greater than the carrier concentration of the drift layer, and wherein the first region of n-type silicon carbide has a higher carrier concentration than a carrier concentration of the drift layer and has a lower carrier concentration than the carrier concentration of the third regions of n-type silicon carbide; source contacts on portions of the second regions of n-type silicon carbide; a gate contact on the oxide layer; and a drain contact on the drift layer opposite the oxide layer. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A silicon carbide metal-oxide semiconductor field effect transistor comprising:
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an n-type silicon carbide drift layer; spaced apart p-type silicon carbide well regions; and an n-type silicon carbide limiting region disposed between the well regions and the drift layer, wherein the n-type limiting region comprises a first portion disposed in close proximity to respective floors of the well regions and a second portion disposed in close proximity to respective sidewalls of the well regions, and wherein the first portion has a carrier concentration greater than a carrier concentration of the second portion. - View Dependent Claims (24, 25)
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Specification