Semiconductor structure including vias

• US 7,221,034 B2
• Filed: 02/27/2004
• Issued: 05/22/2007
• Est. Priority Date: 02/27/2004
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Ahrens, Carsten, Ma, Gordon
• Primary Examiner(s): Cao; Phat X.
• Application Number:
  US10/789,478
• Publication Number:
  US 20050189588A1
• Time in Patent Office: 1,180 Days
• Field of Search: 257/502, 257/503, 257/758
• US Class Current: 257/502
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/585 comprising conductive layers or plates or strips or rods or rings H01L23/60, H01L23/62, H01L23/64, H01L23/66 take precedence
• CPC Class Codes: H01L 23/60 Protection against electrostatic charges or discharges, e.g. Faraday shields
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/4175 for lateral devices where the connection to the source or drain region is done through at least one part of the semiconductor substrate thickness, e.g. with connecting sink or with via-hole
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device may comprise a semiconductor substrate having a top and a bottom surface, first and second insulating layer deposited on the top surface of the substrate, a runner arranged on top of the second insulator layer, a backside metal layer deposited on the bottom surface of the substrate, a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner, and a second via extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having a top and a bottom surface,

first and second insulating layers deposited on the top surface of said substrate,

a runner arranged on top of the second insulator layer,

a backside metal layer deposited on the bottom surface of the substrate,

a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner,

a second via structure extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner, and

barrier metal layers arranged between the first and second vias, between the runner and the second via, and between the first via and the backside metal layer.

2. The semiconductor device as claimed in claim 1, wherein the second via has a smaller footprint than the first via and a plurality of second vias are arranged between the first via and the runner.

3. The semiconductor device as claimed in claim 1, wherein said barrier metal layer between the first and second vias has a cross-sectional profile of a saucer.

4. The semiconductor device as claimed in claim 3, wherein the bottom barrier metal layer comprises side walls that enclose said via.

5. The semiconductor device as claimed in claim 3, wherein the barrier metal layer between the first via and the second via comprises side walls that are spaced apart from said via.

6. The semiconductor device as claimed in claim 1, wherein the barrier metal layer between the first via and the second via consists of Titanium-Titanium nitride.

7. The semiconductor device as claimed in claim 1, wherein the barrier metal layer between the runner and the second via and the barrier metal layer between the backside layer and the first via consist of Titanium-Platinum.

8. The semiconductor device as claimed in claim 1, wherein the second via is filled with tungsten.

9. The semiconductor device as claimed in claim 1, wherein the first via is filled with Tungsten or copper.

10. The semiconductor device as claimed in claim 1, wherein the substrate comprises a p+ substrate and p−

epitaxial layer.

11. The semiconductor device as claimed in claim 1, wherein first and second via structures are arranged between a first and second stage of an integrated device for electromagnetic and/or thermal de-coupling.

12. The semiconductor device as claimed in claim 11, wherein the first stage is an input transistor stage and the second stage is a power transistor output stage.

13. The semiconductor device as claimed in claim 2, wherein the first via structure is extended in such a way that it at least partly surround a first device formed within said semiconductor device for electromagnetic and/or thermal de-coupling.

14. The semiconductor device as claimed in claim 13, wherein the first via structure is extended in such a way that it at least completely surrounds said first device.

15. The semiconductor device as claimed in claim 13, wherein the first and second via structures are extended to form a grid including cells in which certain semiconductor devices are formed.

16. The semiconductor device as claimed in claim 13, wherein said first device includes an active semiconductor structure.

17. The semiconductor device as claimed in claim 13, wherein said first device includes a passive semiconductor structure.

18. The semiconductor device as claimed in claim 13, wherein the first device is shielded from a second device and the first device is coupled with the second device through at least one electrical coupling.

19. The semiconductor device as claimed in claim 18, wherein the second via structure comprises an opening for providing a passageway for the electrical coupling.

20. The semiconductor device as claimed in claim 18, wherein the electrical coupling is arranged in a first or second metal layer.

21. The semiconductor device as claimed in claim 1, wherein the first and second via structures are arranged within a field effect transistor structure having a source region, a drain region and a gate, in such a way that the first via couples the source region with the backside layer.

22. A semiconductor device comprising:

a semiconductor substrate having a top and a bottom surface,

first and second insulating layers deposited on the top surface of said substrate,

a runner arranged on top of the second insulator layer,

a backside metal layer deposited on the bottom surface of the substrate,

a first via structure extending from the bottom surface of the substrate to the top of the first insulating layer between the backside layer and the runner,

a second via structure extending from the top of the first insulating layer to the top of the second insulating layer between the first via and the runner, wherein the first and second via structures are arranged within a field effect transistor structure having a source region, a drain region and a gate, in such a way that the first via couples the source region with the backside layer.

23. The semiconductor device as claimed in claim 22, further comprising barrier metal layers arranged between the first and second vias, between the runner and the second via, and between the first via and the backside metal layer.

24. The semiconductor device as claimed in claim 22, wherein the second via has a smaller footprint than the first via and a plurality of second vias are arranged between the first via and the runner.

25. The semiconductor device as claimed in claim 22, wherein said barrier metal layer between the first and second vias has a cross-sectional profile of a saucer.

26. The semiconductor device as claimed in claim 25, wherein the bottom barrier metal layer comprises side walls that enclose said via.

27. The semiconductor device as claimed in claim 25, wherein the barrier metal layer between the first via and the second via comprises side walls that are spaced apart from said via.

28. The semiconductor device as claimed in claim 22, wherein the barrier metal layer between the first via and the second via consists of Titanium-Titanium nitride.

29. The semiconductor device as claimed in claim 22, wherein the barrier metal layer between the runner and the second via and the barrier metal layer between the backside layer and the first via consist of Titanium-Platinum.

30. The semiconductor device as claimed in claim 22, wherein the second via is filled with tungsten.

31. The semiconductor device as claimed in claim 22, wherein the first via is filled with Tungsten or copper.

32. The semiconductor device as claimed in claim 22, wherein the substrate comprises a p+ substrate and p−

epitaxial layer.

33. The semiconductor device as claimed in claim 22, wherein first and second via structures are arranged between a first and second stage of an integrated device for electromagnetic and/or thermal de-coupling.

34. The semiconductor device as claimed in claim 33, wherein the first stage is an input transistor stage and the second stage is a power transistor output stage.

35. The semiconductor device as claimed in claim 24, wherein the first via structure is extended in such a way that it at least partly surround a first device formed within said semiconductor device for electromagnetic and/or thermal de-coupling.

36. The semiconductor device as claimed in claim 35, wherein the first via structure is extended in such a way that it at least completely surrounds said first device.

37. The semiconductor device as claimed in claim 35, wherein the first and second via structures are extended to form a grid including cells in which certain semiconductor devices are formed.

38. The semiconductor device as claimed in claim 35, wherein said first device includes an active semiconductor structure.

39. The semiconductor device as claimed in claim 35, wherein said first device includes a passive semiconductor structure.

40. The semiconductor device as claimed in claim 35, wherein the first device is shielded from a second device and the first device is coupled with the second device through at least one electrical coupling.

41. The semiconductor device as claimed in claim 40, wherein the second via structure comprises an opening for providing a passageway for the electrical coupling.

42. The semiconductor device as claimed in claim 40, wherein the electrical coupling is arranged in a first or second metal layer.

43. The semiconductor device as claimed in claim 22, further comprising at least one drain runner arranged on top of the first and/or second oxide layer above said drain region and on one side of the first and second via structures, and at least one gate runner arranged on top of the first and/or second oxide layer on the other side of the first and second via structures.