Programmable microcontroller architecture (mixed analog/digital)

• US 7,221,187 B1
• Filed: 03/16/2004
• Issued: 05/22/2007
• Est. Priority Date: 10/26/2000
• Status: Expired due to Term

• Current Assignee: Monterey Research, LLC (Vector Capital Corporation)
• Original Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Inventors: Snyder, Warren, Mar, Monte
• Primary Examiner(s): Tran, Anh Q.
• Application Number:
  US10/803,030
• Time in Patent Office: 1,162 Days
• Field of Search: 326 37- 47
• US Class Current: 326/41
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/32 Means for saving power
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06G 7/06 Programming arrangements, e.g. plugboard for interconnecting functional units of the computer; Digital programming hybrid computers G06J
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03K 19/08 using semiconductor devices H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12
• CPC Class Codes: H03K 19/173 using elementary logic circuits as components
• CPC Class Codes: H03K 19/1733 Controllable logic circuits H03K19/177 takes precedence
• CPC Class Codes: H03K 19/177 arranged in matrix form
• CPC Class Codes: H03K 19/17736 Structural details of routing resources
• CPC Class Codes: H03K 19/17748 Structural details of configuration resources
• CPC Class Codes: H03K 3/012 Modifications of generator to improve response time or to decrease power consumption
• CPC Class Codes: H03K 3/014 Modifications of generator to ensure starting of oscillations
• CPC Class Codes: H03K 3/02315 Stabilisation of output, e.g. using crystal

Abstract

A microcontroller with a mixed analog/digital architecture including multiple digital programmable blocks and multiple analog programmable blocks in a communication array having a programmable interconnect structure. The single chip design is implemented by integration of programmable digital and analog circuit blocks that are able to communicate with each other. Robust analog and digital blocks that are flash memory programmable can be utilized to realize complex design applications that otherwise would require multiple chips and/or separate applications. The programmable chip architecture includes a novel array having programmable digital blocks that can communicate with programmable analog blocks using a programmable interconnect structure. The programmable analog array contains a complement of Continuous Time (CT) blocks and a complement of Switched Capacitor (SC) blocks that can communicate together. The analog blocks consist of multi-function circuits programmable for one or more different analog functions, and fixed function circuits programmable for a fixed function with variable parameters. The digital blocks include standard multi-function circuits and enhanced circuits having functions not included in the standard digital circuits. The programmable array is programmed by flash memory and programming allows dynamic reconfiguration. That is, “on-the-fly” reconfiguration of the programmable blocks is allowed. The programmable analog array with both Continuous Time analog blocks and Switched Capacitor analog blocks are offered on a single chip along with programmable digital blocks. The programmable interconnect structure provides for communication of input/output data between all analog and digital blocks.

Claims

1. A circuit comprising:

a plurality of analog circuit blocks;

a plurality of digital circuit blocks;

a bus coupling analog input/output data and digital input/output data for the plurality of analog circuit blocks and the plurality of digital circuit blocks; and

a system clock for controlling the coupling of the analog input/output data and the digital input output data to the bus.

2. A circuit according to claim 1 further comprising:

a programmable interconnect structure coupled to the plurality of analog circuit blocks and the plurality of digital circuit blocks.

3. A circuit according to claim 2 wherein the programmable interconnect structure is configured to dynamically reconfigure the plurality of analog circuit blocks and the plurality of digital circuit blocks to implement one of a plurality of functions.

4. A circuit according to claim 1 wherein the circuit comprises a single integrated circuit semiconductor chip.

5. A circuit according to claim 1 wherein the analog circuit blocks comprises at least one continuous time analog circuit.

6. A circuit according to claim 1 wherein the analog circuit blocks comprises at least one switched capacitor analog circuit.

7. A microcontroller comprising:

a plurality of programmable analog circuit blocks;

a plurality of programmable digital circuit blocks;

a programmable interconnect coupling the analog circuit blocks and the digital circuit blocks;

a bus coupling analog input/output data and digital input/output data for the analog circuit blocks and the digital circuit blocks; and

a system clock for controlling the bus.

8. A microcontroller according to claim 7 wherein one of the digital circuit blocks is configured to implement logical operations.

9. A microcontroller according to claim 7 wherein one of the digital circuit blocks is configured to implement computational operations.

10. A microcontroller according to claim 7 wherein the programmable interconnect structure and the programmable analog circuit blocks and the plurality of programmable digital circuit blocks are constructed on a semiconductor chip.

11. A microcontroller according to claim 7 wherein the programmable analog circuit blocks comprise at least one continuous time analog circuit block.

12. A microcontroller according to claim 7 wherein the programmable analog circuit blocks comprise at least one switched capacitor analog circuit block.

13. A microcontroller according to claim 7 wherein the programmable digital circuit blocks comprise at least one digital multi-function circuit block having a first set of digital functions and at least one digital multi-function circuit block having a second set of digital functions different from the first set.

14. A method of providing a dynamically programmable analog/digital communication interface circuit, comprising:

configuring a plurality of programmable analog circuit blocks to implement at least one of a plurality of analog functions,

configuring a plurality of programmable digital circuit blocks to implement at least one of a plurality of digital functions,

configuring a routing matrix to couple analog data and digital data between the programmable analog circuit blocks and the programmable digital circuit blocks; and

transferring data via a bus independent of the routing matrix and in accordance with at least one system clock.

15. The method according to claim 14 wherein flash memory is used to program the routing matrix and the plurality of programmable analog circuit blocks and the plurality of programmable digital circuit blocks and to enable dynamic circuit reconfiguration.

16. The method according to claim 14 wherein the programmable analog circuit blocks comprise at least one continuous time analog circuit and at least one switched capacitor analog circuit.

17. The method according to claim 14 wherein the programmable digital circuit blocks comprise at least one standard digital multi-function circuit having a first set of digital functions and at least one enhanced digital multi-function circuit having at least one function differing from the first set of digital functions.

18. The method according to claim 14 wherein the programmable analog circuit blocks comprise at least one multi-function circuit programmable for at least one of the plurality of analog functions and at least one fixed function circuit programmable for a fixed function with at least one of a number of different parameters.

19. The method according to claim 14 wherein the plurality of digital functions comprises logical operations.

20. The method according to claim 14 wherein the plurality of digital functions comprises computational operations.