Memory array incorporating memory cells arranged in NAND strings

• US 7,221,588 B2
• Filed: 12/05/2003
• Issued: 05/22/2007
• Est. Priority Date: 12/05/2003
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk 3D LLC (Western Digital Corporation)
• Inventors: Scheuerlein, Roy E., Fasoli, Luca G., Nallamothu, Sucheta, Mahajani, Maitreyee, Walker, Andrew J., Chen, En-Hsing
• Primary Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US10/729,843
• Publication Number:
  US 20050122779A1
• Time in Patent Office: 1,264 Days
• Field of Search: 365/185.11, 365/185.13 X, 365/185.17 O, 365/185.13, 365/185.17, 257/314, 257/315, 257/316
• US Class Current: 365/185.17
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure

Abstract

An exemplary NAND string memory array includes at least one plane of memory cells, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, and NAND strings including a series select device at each end thereof. Another exemplary NAND string memory array includes a group of more than four adjacent NAND strings within the same memory block each associated with a respective global bit line not shared by the other NAND string of the group. Another exemplary NAND string memory array includes NAND strings on identical pitch as their respective global bit lines.

Claims

1. An integrated circuit comprising a memory array having at least two planes of memory cells formed above a substrate, said memory cells comprising thin film modifiable conductance switch devices and which cells are arranged in a plurality of series-connected NAND strings, said memory array comprising a first plurality of zias, each of said first plurality of zias respectively coupling a first end of a respective NAND string on each of two or more memory planes to a respective global bit line, and said memory array further comprising a second plurality of zias, each of said second plurality of zias respectively coupling a second end of a respective NAND string on each of two or more memory planes to an associated bias node.

2. The integrated circuit of claim 1 wherein said switch devices include a charge storage dielectric.

3. The integrated circuit of claim 2 wherein said charge storage dielectric comprises an oxide-nitride-oxide dielectric stack.

4. The integrated circuit of claim 1 wherein said switch devices include a floating gate electrode.

5. The integrated circuit of claim 1 wherein adjacent NAND strings are respectively coupled to a respective global bit line by way of a respective zia structure having a pitch matching that of the NAINI) strings.

6. The integrated circuit of claim 1 further comprising NAND strings including a series select device at each end thereof.

7. The integrated circuit of claim 1 wherein the substrate comprises a monocrystalline substrate including circuitry which is coupled to the memory array.

8. The integrated circuit of claim 1 wherein the substrate comprises a polycrystalline substrate.

9. The integrated circuit of claim 1 wherein the substrate comprises an insulating substrate.

10. The integrated circuit of claim 1 wherein the thin film modifiable conductance switch devices comprise silicon nanoparticles.

11. The integrated circuit of claim 1 wherein the thin film modifiable conductance switch devices comprise a polarizable material.

12. The integrated circuit of claim 1 wherein the thin film modifiable conductance switch devices comprise a ferroelectric material.

13. The integrated circuit of claim 1 wherein the thin film modifiable conductance switch devices comprise transistors having a depletion mode threshold voltage for at least one of two data states.

14. The integrated circuit of claim 1 embodied in computer readable descriptive form suitable for design, test, or fabrication of the integrated circuit.

15. The integrated circuit of claim 1 wherein:

adjacent NAND strings share a single zia coupled to an associated bias node.