Multiple level programming in a non-volatile memory device

• US 7,221,592 B2
• Filed: 02/25/2005
• Issued: 05/22/2007
• Est. Priority Date: 02/25/2005
• Status: Expired due to Fees

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Nazarian, Hagop A.
• Primary Examiner(s): Zarabian; Amir
• Assistant Examiner(s): Graham; Kretelia
• Application Number:
  US11/065,986
• Publication Number:
  US 20060193169A1
• Time in Patent Office: 816 Days
• Field of Search: 365/185.19, 365/185.18
• US Class Current: 365/185.19
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/3418 Disturbance prevention or evaluation; Refreshing of disturbed memory data
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 2211/5648 Multilevel memory programming, reading or erasing operations wherein the order or sequence of the operations is relevant

Abstract

The programming method of the present invention minimizes program disturb by initially programming cells on the same wordline with the logical state having the highest threshold voltage. The remaining cells on the wordline are programmed to their respective logical states in order of decreasing threshold voltage levels.

Claims

1. A method for programming a multiple level NAND non-volatile memory device comprising a plurality of rows coupled to wordlines and a plurality of columns, each coupled to a bitline, the method comprising:

programming a first cell, coupled to a selected wordline and a selected bitline, with a first state having a highest threshold voltage distribution of a plurality of states each having a different threshold voltage distribution; and

programming remaining cells that are coupled to the selected wordline in a decreasing order of threshold voltage distributions wherein the selected wordline is biased with a programming voltage and unselected wordlines of the plurality of wordlines are biased at a constant predetermined voltage that is less than the programming voltage and greater than 0V, the selected bitline is biased at 0V, and unselected bitlines are biased at an inhibit voltage.

2. The method of claim 1 wherein the first state is a logical multiple bit “

01”

.

3. The method of claim 1 wherein the inhibit voltage is 1.3V.

4. The method of claim 1 wherein the multiple level memory device is an electrically erasable programmable read only memory.

5. The method of claim 1 wherein the plurality of states in decreasing order of programming voltage levels necessary to program comprises “

01”

, “

00”

, and “

10”

.

6. The method of claim 1 wherein the first cell and the remaining cells are part of a plurality of memory pages coupled to a wordline in which a first page is programmed with two highest distributions, and a second page is programmed with lower distributions.

7. The method of claim 6 wherein a program disturb for the first cell is reduced when the remaining cells are programmed.

8. A method for programming a multiple level NAND flash memory device comprising a plurality of rows and series column strings of cells, each row having a plurality of cells coupled to a wordline of a plurality of wordlines, each column having a series string of a plurality of cells coupled to a bitline, and each cell programmable with one of a plurality of states, each state having a different threshold voltage distribution, the method comprising:

programming the plurality of cells of a selected wordline such that each cell having a highest threshold voltage distribution is programmed first and remaining cells of the selected wordline to be programmed are programmed in decreasing levels of threshold voltage distributions wherein the selected wordline is biased with a programming voltage and unselected wordlines of the plurality of wordlines are biased at a constant predetermined voltage that is less than the programming voltage and greater than 0V, a selected bitline is biased at 0V, and unselected bitlines are biased at an inhibit voltage that is greater than 0V.

9. The method of claim 8 wherein the plurality of states comprise 11, 10, 00, and 01 such that state 01 requires the highest programming voltage.

10. The method of claim 9 wherein state 11 is an erased state.

11. A method for programming a multiple level NAND flash memory device comprising a plurality of rows and columns of cells, each row having a plurality of cells coupled to a wordline, each column having a series string of a plurality of cells coupled to a bitline, and each cell programmable with one of a plurality of states each state having a different programming voltage, the method comprising:

initially programming each cell, of a selected wordline, to be programmed with a state having a first programming voltage;

programming each cell, of the selected wordline, to be programmed with a state having a second programming voltage; and

programming each cell, of the selected wordline, to be programmed with a state having a third programming voltage such that the third programming voltage is less than the second programming voltage that is less than the first programming voltage and wherein the selected wordline is biased with a programming voltage and unselected wordlines of the plurality of wordlines are biased at a constant predetermined voltage that is less than the programming voltage and greater than 0V, selected bitlines are biased at 0V, and unselected bitlines are biased at an inhibit voltage that is greater than 0V.