Non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation)

• US 7,221,714 B2
• Filed: 05/27/2003
• Issued: 05/22/2007
• Est. Priority Date: 05/12/2003
• Status: Expired due to Fees

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: Shen, Ba-Zhong, Jones, Christopher R., Tran, Hau Thien, Cameron, Kelly Brian
• Primary Examiner(s): Payne; David C.
• Assistant Examiner(s): Lu; Jia
• Application Number:
  US10/446,318
• Publication Number:
  US 20040228419A1
• Time in Patent Office: 1,456 Days
• Field of Search: 375/265, 375/261, 375/260
• US Class Current: 375/265
• CPC Class Codes: H04L 1/0041 Arrangements at the transmitter end
• CPC Class Codes: H04L 1/006 Trellis-coded modulation
• CPC Class Codes: H04L 1/0066 Parallel concatenated codes
• CPC Class Codes: H04L 2001/0097 Relays
• CPC Class Codes: H04L 27/0008 arrangements for allowing a transmitter or receiver to use more than one type of modulation negotiating modulation type for two-way transmission paths H04L5/1453

Abstract

Non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation). A non-systematic and non-linear PC-TCM code is presented that provides quite comparable performance to turbo encoding using only systematic and linear trellis codes (e.g., convolutional codes). The non-systematic and non-linear PC-TCM described herein may be modified to support a wide variety of code rates (e.g., rate 2/3, 5/6, 8/9, and 3/4 among other rates) and also a wide modulation types (e.g., 8 PSK (8 Phase Shift Key) and 16 QAM (16 Quadrature Amplitude Modulation) among other modulation types). In one embodiment, a non-systematic and non-linear PC-TCM presented herein comes to within approximately 0.15 dB of a systematic and linear turbo code. A design approach is presented that allows for the design of such non-systematic and non-linear PC-TCM codes and several exemplary embodiments are also presented that have been designed according to these presented principles.

Claims

1. A non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation) code design method, the method comprising:

for a trellis, identifying a fixed output state distribution and a plurality of fixed state transitions;

for the trellis, identifying a corresponding input state distribution to support non-systematic and non-linear trellis encoding using the trellis;

identifying a plurality of possible non-systematic and non-linear PC-TCM encoders capable of performing the non-systematic and non-linear trellis encoding using the trellis according to the identified, corresponding input state distribution, the fixed output state distribution, and the plurality of fixed state transitions;

for each non-systematic and non-linear PC-TCM encoder of the plurality of possible non-systematic and non-linear PC-TCM encoders, identifying a symbol mapper, operable to map output symbols to a corresponding constellation, that provides for a best performance in terms of a lowest BER (Bit Error Rate) for output bits that are grouped into the output symbols;

determining the overall performance of each non-systematic and non-linear PC-TCM encoder of the plurality of possible non-systematic and non-linear PC-TCM encoders in terms of the E_b/N₀ (ratio of energy per bit E_b to the Spectral Noise Density N₀) waterfall parts and corresponding BERs; and

selecting a non-systematic and non-linear PC-TCM encoder of the plurality of possible non-systematic and non-linear PC-TCM encoders that provides the lowest E_b/N₀ waterfall part with the lowest BER floor.

2. The method of claim 1, wherein:

the selected non-systematic and non-linear PC-TCM encoder includes a rate k/k+n upper constituent encoder and a rate k/k+n lower constituent encoder;

input provided to the rate k/k+n lower constituent encoder passes through an interleaver that is operable to perform sub-block interleaving on groups of input bits taken during alternate clock cycles; and

k and n are both integers.

3. The method of claim 2, wherein:

during alternate clock cycles, the symbol mapper alternatively maps output symbols generated by the rate k/k+n upper constituent encoder and the rate k/k+n lower constituent encoder, respectively.

4. The method of claim 2, wherein:

the rate k/k+n upper constituent encoder and the rate k/k+n lower constituent encoder are both rate 2/3 constituent encoders, rate 5/6 constituent encoders, rate 8/9 constituent encoders, or rate 3/4 constituent encoders.

5. The method of claim 4;

wherein;

each of the rate 5/6 constituent encoders and the rate 8/9 constituent encoders is implemented using a rate 2/3 constituent encoder in conjunction with puncturing of at least output bit.

6. The method of claim 5, wherein:

for the rate 5/6 constituent encoders, the output bits are grouped to simultaneously form 2 separate output symbols of 3 bits each; and

for the rate 8/9 constituent encoders, the output bits are grouped to simultaneously form 3 separate output symbols of 3 bits each.

7. The method of claim 4, wherein:

the output bits include at least one encoded bit and at least one uncoded bit.

8. The method of claim 2, wherein:

the trellis is an 8 state trellis;

the rate k/k+n upper constituent encoder and the rate k/k+n lower constituent encoder are both rate 2/3 constituent encoders; and

each of the rate 2/3 upper constituent encoder and the rate 2/3 lower constituent encoder encodes input symbols including 2 bits each and generates output symbols including 3 bits each.

9. The method of claim 1, wherein:

the selected non-systematic and non-linear PC-TCM encoder is a rate 2/3 non-systematic and non-linear PC-TCM encoder that maps output symbols to an 8 PSK (8 Phase Shift Key) shaped constellation according to the identified symbol mapper;

for a communication channel having a Shannon'"'"'s limit capacity of approximately 2 bits per second per Hz (Hertz), the lowest E_b/N₀ waterfall part of the rate 2/3 non-systematic and non-linear PC-TCM encoder ranges between approximately 3.45 dB (decibels) at a BER of approximately 2×

10<sup>−

3</sup> and approximately 3.65 db at a BER of approximately 3×

10<sup>−

7</sup>; and

the BER floor of the rate 2/3 non-systematic and non-linear PC-TCM encoder ranges between approximately 2×

10<sup>−

7</sup> and approximately 3×

10<sup>−

7</sup>.

10. The method of claim 1, further comprising:

implementing the selected non-systematic and non-linear PC-TCM encoder within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, and a uni-directional communication system, a bi-directional communication system, and a one to many communication system.

11. A non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation) code design method, the method comprising:

for a trellis, identifying a fixed output state distribution and a plurality of fixed state transitions;

for the trellis, identifying a corresponding input state distribution to support non-systematic and non-linear trellis encoding using the trellis;

identifying a plurality of possible non-systematic and non-linear PC-TCM encoders capable of performing the non-systematic and non-linear trellis encoding using the trellis according to the identified, corresponding input state distribution, the fixed output state distribution, and the plurality of fixed state transitions;

for each non-systematic and non-linear PC-TCM encoder of the plurality of possible non-systematic and non-linear PC-TCM encoders, identifying a symbol mapper, operable to map output symbols to a corresponding constellation, that provides for a best performance in terms of a lowest BER (Bit Error Rate) for output bits that are grouped into the output symbols;

determining the overall performance of each non-systematic and non-linear PC-TCM encoder of the plurality of possible non-systematic and non-linear PC-TCM encoders in terms of the E_b/N₀ (ratio of energy per bit E_b to the Spectral Noise Density N₀) waterfall parts and corresponding BERs;

selecting a non-systematic and non-linear PC-TCM encoder of the plurality of possible non-systematic and non-linear PC-TCM encoders that provides the lowest E_b/N₀ waterfall part with the lowest BER floor;

the selected non-systematic and non-linear PC-TCM encoder includes a rate k/k+n upper constituent encoder and a rate k/k+n lower constituent encoder;

input provided to the rate k/k+n lower constituent encoder passes through an interleaver that is operable to perform sub-block interleaving on groups of input bits taken during alternate clock cycles;

during alternate clock cycles, the symbol mapper alternatively maps output symbols generated by the rate k/k+n upper constituent encoder and the rate k/k+n lower constituent encoder, respectively; and

wherein k and n are both integers.

12. The method of claim 11, wherein:

the rate k/k+n upper constituent encoder and the rate k/k+n lower constituent encoder are both rate 2/3 constituent encoders, rate 5/6 constituent encoders, rate 8/9 constituent encoders, or rate 3/4 constituent encoders;

each of the rate 5/6 constituent encoders and the rate 8/9 constituent encoders is implemented using a rate 2/3 constituent encoder in conjunction with puncturing of at least output bit;

for the rate 5/6 constituent encoders, the output bits are grouped to simultaneously form 2 separate output symbols of 3 bits each; and

for the rate 8/9 constituent encoders, the output bits are grouped to simultaneously form 3 separate output symbols of 3 bits each.

13. The method of claim 11, wherein:

the trellis is an 8 state trellis;

the rate k/k+n upper constituent encoder and the rate k/k+n lower constituent encoder are both rate 2/3 constituent encoders; and

each of the rate 2/3 upper constituent encoder and the rate 2/3 lower constituent encoder encodes input symbols including 2 bits each and generates output symbols including 3 bits each.

14. The method of claim 11, wherein:

the selected non-systematic and non-linear PC-TCM encoder is a rate 2/3 non-systematic and non-linear PC-TCM encoder that maps output symbols to an 8 PSK (8 Phase Shift Key) shaped constellation according to the identified symbol mapper;

for a communication channel having a Shannon'"'"'s limit capacity of approximately 2 bits per second per Hz (Hertz), the lowest E_b/N₀ waterfall part of the rate 2/3 non-systematic and non-linear PC-TCM encoder ranges between approximately 3.45 dB (decibels) at a BER of approximately 2×

10<sup>−

3</sup> and approximately 3.65 dB at a BER of approximately 3×

10<sup>−

7</sup>; and

the BER floor of the rate 2/3 non-systematic and non-linear PC-TCM encoder ranges between approximately 2×

10<sup>−

7</sup> and approximately 3×

10<sup>−

7</sup>.

15. The method of claim 11, further comprising:

implementing the selected non-systematic and non-linear PC-TCM encoder within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, and a uni-directional communication system, a bi-directional communication system, and a one to many communication system.

16. A non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation) encoder, the encoder comprising:

a rate k/k+n upper constituent encoder that is operable to receive input bits and to generate a first plurality of output bits there from;

a sub-block interleaver that is operable to interleave input bit sub-blocks selected during alternate clock cycles;

a rate k/k+n lower constituent encoder that is operable to receive the interleaved input bit sub-blocks from the sub-block interleaver and to generate a second plurality of output bits there from;

during alternate clock cycles, a symbol mapper that alternatively selects and groups bits from the first plurality of output bits and the second plurality of output bits to generate a plurality of output symbols;

wherein the symbol mapper maps output symbols from the plurality of output symbols to a constellation according to a symbol mapping;

wherein each of the rate k/k+n upper constituent encoder and the rate k/k+n lower constituent encoder employs a trellis having a fixed output state distribution and a plurality of fixed state transitions;

wherein a corresponding input state distribution for the trellis is identified and employed to support non-systematic and non-linear trellis encoding within each of the rate k/k+n upper constituent encoder and the rate k/k+n lower constituent encoder; and

wherein k and n are both integers.

17. The encoder of claim 16, wherein:

the rate k/k+n upper constituent encoder and the rate k/k+n lower constituent encoder are both rate 2/3 constituent encoders.

18. The encoder of claim 16, wherein:

the symbol mapper selects and employs at least one uncoded bit when generating at least one output symbol of the plurality of output symbols.

19. The encoder of claim 16, wherein:

the rate k/k+n upper constituent encoder and the rate k/k+n lower constituent encoder are both rate 5/6 constituent encoders, rate 8/9 constituent encoders, or rate 3/4 constituent encoders.

20. The encoder of claim 16, wherein:

each of the rate 5/6 constituent encoders and the rate 8/9 constituent encoders is implemented using a rate 2/3 constituent encoder in conjunction with puncturing of at least output bit.

21. The encoder of claim 20, wherein:

for the rate 5/6 constituent encoders, the output bits are grouped to simultaneously form 2 separate output symbols of 3 bits each;

for the rate 8/9 constituent encoders, the output bits are grouped to simultaneously form 3 separate output symbols of 3 bits each;

the output symbols of 3 bits each are 8 PSK (8 Phase Shift Key) output symbols; and

the symbol mapper is an 8 PSK symbol mapper.

22. The encoder of claim 16, wherein:

for the rate 3/4 constituent encoders, three output bits and one uncoded bit are grouped to form an output symbols having 4 bits;

the output symbol having 4 bits is a 16 QAM (16 Quadrature Amplitude Modulation) output symbol; and

the symbol mapper is a 16 QAM symbol mapper.

23. The encoder of claim 16, wherein:

the trellis is an 8 state trellis;

the rate k/k+n upper constituent encoder and the rate k/k+n lower constituent encoder are both rate 2/3 constituent encoders; and

each of the rate 2/3 upper constituent encoder and the rate 2/3 lower constituent encoder encodes input symbols including 2 bits each and generates output symbols including 3 bits each.

24. The encoder of claim 16, wherein:

the non-systematic and non-linear PC-TCM encoder is a rate 2/3 non-systematic and non-linear PC-TCM encoder;

the symbol mapper maps output symbols to an 8 PSK (8 Phase Shift Key) shaped constellation;

for a communication channel having a Shannon'"'"'s limit capacity of approximately 2 bits per second per Hz (Hertz), the lowest E_b/N₀ (ratio of energy per bit E_b to the Spectral Noise Density N₀) waterfall part of the rate 2/3 non-systematic and non-linear PC-TCM encoder ranges between approximately 3.45 dB (decibels) at a BER (Bit Error Rate) of approximately 2×

10<sup>−

3</sup> and approximately 3.65 dB at a BER of approximately 3×

10<sup>−

7</sup>; and

the BER floor of the rate 2/3 non-systematic and non-linear PC-TCM encoder ranges between approximately 2×

10<sup>−

7</sup> and approximately 3×

10<sup>−

7</sup>.

25. The encoder of claim 16, wherein:

the encoder is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, and a uni-directional communication system, a bi-directional communication system, and a one to many communication system.

26. A rate 2/3 non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation) encoder, the encoder comprising:

a rate 2/3 upper constituent encoder that is operable to receive input bits and to generate a first plurality of output bits there from;

a sub-block interleaver that is operable to interleave input bit sub-blocks selected during alternate clock cycles, the input bit sub-blocks being generated from an input bit block;

a rate 2/3 lower constituent encoder that is operable to receive the interleaved input bit sub-blocks from the sub-block interleaver and to generate a second plurality of output bits there from;

during alternate clock cycles, a symbol mapper that alternatively selects and groups bits from the first plurality of output bits and the second plurality of output bits to generate a plurality of output symbols;

the symbol mapper maps output symbols from the plurality of output symbols to a constellation according to a symbol mapping;

wherein each of the rate 2/3 upper constituent encoder and the rate 2/3 lower constituent encoder employs a trellis having a fixed output state distribution and a plurality of fixed state transitions; and

wherein a corresponding input state distribution for the trellis is identified and employed to support non-systematic and non-linear trellis encoding within each of the rate 2/3 upper constituent encoder and the rate 2/3 lower constituent encoder.

27. The encoder of claim 26, wherein:

the trellis is an 8 state trellis; and

each of the rate 2/3 upper constituent encoder and the rate 2/3 lower constituent encoder encodes input symbols including 2 bits each and generates output symbols including 3 bits each.

28. The encoder of claim 26, wherein:

the symbol mapper maps output symbols to an 8 PSK (8 Phase Shift Key) shaped constellation;

for a communication channel having a Shannon'"'"'s limit capacity of approximately 2 bits per second per Hz (Hertz), the lowest E_b/N₀ (ratio of energy per bit E_b to the Spectral Noise Density N₀) waterfall part of the rate 2/3 non-systematic and non-linear PC-TCM encoder ranges between approximately 3.45 dB (decibels) at a BER (Bit Error Rate) of approximately 2×

10<sup>−

3</sup> and approximately 3.65 dB at a BER of approximately 3×

10<sup>−

7</sup>; and

the BER floor of the rate 2/3 non-systematic and non-linear PC-TCM encoder ranges between approximately 2×

10<sup>−

7</sup> and approximately 3×

10<sup>−

7</sup>.

29. The encoder of claim 26, wherein:

the encoder is implemented within at least one of a satellite communication system, an HDTV (High Definition Television) communication system, a cellular communication system, a microwave communication system, a point-to-point communication system, and a uni-directional communication system, a bi-directional communication system, and a one to many communication system.

30. A rate 5/6 and two 8-PSK non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation) encoder, the encoder comprising:

a rate 5/6 upper constituent encoder that is operable to receive input bits and to generate a first plurality of output bits there from;

a sub-block interleaver that is operable to interleave input bit sub-blocks selected during alternate clock cycles, the input bit sub-blocks being generated from an input bit block;

a rate 5/6 lower constituent encoder that is operable to receive the interleaved input bit sub-blocks from the sub-block interleaver and to generate a second plurality of output bits there from;

during alternate clock cycles, a symbol mapper that alternatively selects and groups bits from the first plurality of output bits and the second plurality of output bits to generate a plurality of output symbols;

the symbol mapper maps output symbols from the plurality of output symbols to a constellation according to a symbol mapping;

wherein each of the rate 5/6 upper constituent encoder and the rate 5/6 lower constituent encoder employs a trellis having a fixed output state distribution and a plurality of fixed state transitions;

wherein a corresponding input state distribution for the trellis is identified and employed to support non-systematic and non-linear trellis encoding within each of the rate 5/6 upper constituent encoder and the rate 5/6 lower constituent encoder;

wherein each of the rate 5/6 upper constituent encoder and the rate 5/6 lower constituent encoder includes a rate 2/3 non-systematic encoder;

wherein the trellis is an 8 state trellis;

wherein each of the rate 2/3 non-systematic encoders within the rate 5/6 upper constituent encoder and the rate 5/6 lower constituent encoder encodes input symbols including 2 bits each and generates output symbols including 3 bits each; and

wherein the plurality of output symbols includes 2 output symbols of 3 bits each such that the 2 output symbols are 8 PSK (8 Phase Shift Key) symbols.

31. The encoder of claim 30, wherein:

the 2 output symbols are simultaneously generated over a 2 clock cycle period; and

at least one output symbol of the 2 output symbols includes at least one uncoded bit.

32. The encoder of claim 30, wherein:

the 2 output symbols are simultaneously generated over a 2 clock cycle period; and

at least one output bit of the first plurality of output bits and the second plurality of output bits is punctured when forming the 2 output symbols.

33. The encoder of claim 30, wherein:

the symbol mapper maps the 2 output symbols to an 8 PSK (8 Phase Shift Key) shaped constellation using 2 different constellation mappings;

for a communication channel having a Shannon'"'"'s limit capacity of approximately 2.5 bits per second per Hz (Hertz), the lowest E_b/N₀ (ratio of energy per bit E_b to the Spectral Noise Density N₀) waterfall part of the rate 5/6 and 2-8PSK non-systematic and non-linear PC-TCM encoder ranges between approximately 5.5 dB (decibels) at a BER (Bit Error Rate) of approximately 2×

10<sup>−

4</sup> and approximately 5.66 dB at a BER of approximately 2×

10<sup>−

6</sup>; and

the BER floor of the rate 5/6 and 2-8PSK non-systematic and non-linear PC-TCM encoder ranges between approximately 1.75×

10<sup>−

6</sup> and approximately 2×

10<sup>−

6</sup>.

34. A rate 8/9 and 8-PSK non-systematic and non-linear PC-TCM (Parallel Concatenate Trellis Coded Modulation) encoder, the encoder comprising:

a rate 8/9 upper constituent encoder that is operable to receive input bits and to generate a first plurality of output bits there from;

a sub-block interleaver that is operable to interleave input bit sub-blocks selected during alternate clock cycles, the input bit sub-blocks being generated from an input bit block;

a rate 8/9 lower constituent encoder that is operable to receive the interleaved input bit sub-blocks from the sub-block interleaver and to generate a second plurality of output bits there from;

during alternate clock cycles, a symbol mapper that alternatively selects and groups bits from the first plurality of output bits and the second plurality of output bits to generate a plurality of output symbols;

the symbol mapper maps output symbols from the plurality of output symbols to a constellation according to a symbol mapping;

wherein each of the rate 8/9 upper constituent encoder and the rate 8/9 lower constituent encoder employs a trellis having a fixed output state distribution and a plurality of fixed state transitions;

wherein a corresponding input state distribution for the trellis is identified and employed to support non-systematic and non-linear trellis encoding within each of the rate 8/9 upper constituent encoder and the rate 8/9 lower constituent encoder;

wherein each of the rate 8/9 upper constituent encoder and the rate 8/9 lower constituent encoder includes a rate 2/3 non-systematic encoder;

wherein the trellis is an 8 state trellis;

wherein each of the rate 2/3 non-systematic encoders within the rate 8/9 upper constituent encoder and the rate 8/9 lower constituent encoder encodes input symbols including 2 bits each and generates output symbols including 3 bits each; and

wherein the plurality of output symbols includes 3 output symbols of 3 bits each such that the 3 output symbols are 8 PSK (8 Phase Shift Key) symbols.

35. The encoder of claim 34, wherein:

the 3 output symbols are simultaneously generated over a 3 clock cycle period; and

at least one output symbol of the 3 output symbols includes at least one uncoded bit.

36. The encoder of claim 34, wherein:

the 3 output symbols are simultaneously generated over a 3 clock cycle period; and

at least one output bit of the first plurality of output bits and the second plurality of output bits is punctured when forming the 3 output symbols.

37. The encoder of claim 34, wherein:

the symbol mapper maps the 3 output symbols to an 8 PSK (8 Phase Shift Key) shaped constellation using 3 different constellation mappings;

for a communication channel having a Shannon'"'"'s limit capacity of approximately 2.66 bits per second per Hz (Hertz), the lowest E_b/N₀ (ratio of energy per bit E_b to the Spectral Noise Density N₀) waterfall part of the rate 8/9 and 3-8PSK non-systematic and non-linear PC-TCM encoder ranges between approximately 6.55 dB (decibels) at a BER (Bit Error Rate) of approximately 4×

10<sup>−

5</sup> and approximately 6.65 dB at a BER of approximately 1.5×

10<sup>−

6</sup>; and

the BER floor of the rate 8/9 and 3-8PSK non-systematic and non-linear PC-TCM encoder ranges between approximately 1×

10<sup>−

6</sup> and approximately 15×

10<sup>−

6</sup>.